• 22 nm lithography process
  ...g using 22 nm process began in 2008 for memory and 2012 for [[MPU]]s. This technology was replaced by with [[20 nm lithography process|20 nm process]] (HN) in 20 * [[:File:22FFL-2017.pdf|Intel's 22FFL technology]]
  7 KB (891 words) - 09:52, 25 November 2020
• 16 nm lithography process
  ...ain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with [[10 nm lithography process|10 nm process]] in 2 ...2016 TSMC announced a "12nm" process (e.g. 12FFC<info>12nm FinFET Compact Technology</info>) which uses the similar design rules as the 16nm node but a tighter
  4 KB (580 words) - 17:00, 26 March 2019
• 20 nm lithography process
  ...integrated circuit]] manufacturing using 20 nm process began in 2014. This technology superseded by commercial [[16 nm lithography process|16 nm process]]. <tr><th>Technology</th><td>20 nm HK-MG</td></tr>
  4 KB (483 words) - 23:04, 20 May 2018
• 40 nm lithography process
  ...ss began in 2008 by leading semiconductor companies such as [[TSMC]]. This technology superseded by commercial [[32 nm lithography process|32 nm process]] by 201
  2 KB (182 words) - 03:11, 17 August 2023
• 55 nm lithography process
  ...process began in late 2006 by companies such as [[TSMC]] and [[NEC]]. This technology superseded by commercial [[45 nm lithography process|45 nm process]].
  600 bytes (72 words) - 05:54, 20 July 2018
• 65 nm lithography process
  ...integrated circuit]] manufacturing using 65 nm process began in 2005. This technology was superseded by the [[55 nm lithography process|55 nm process]] (HN) / [[
  4 KB (407 words) - 05:55, 20 July 2018
• 130 nm lithography process
  ...ntegrated circuit]] manufacturing using 130 nm process began in 2001. This technology was replaced by with [[110 nm lithography process|110 nm process]] (HN) in * Tyagi, Sunit, et al. "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interco
  5 KB (500 words) - 16:02, 13 May 2020
• 90 nm lithography process
  ...integrated circuit]] manufacturing using 90 nm process began in 2003. This technology was superseded by the [[80 nm lithography process|80 nm process]] (HN) / [[
  3 KB (354 words) - 03:09, 17 August 2023
• 180 nm lithography process
  ...ated circuit]] manufacturing using 180 nm process began in late 1998. This technology was replaced by with [[150 nm lithography process|150 nm process]] (HN) in
  4 KB (413 words) - 03:04, 17 August 2023
• 10 nm lithography process
  ...nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[gate length]] or [[half pitch]]. The 10 nm node is current First introduced between 2017-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 30-40s nm [[
  14 KB (1,903 words) - 06:52, 17 February 2023
• 7 nm lithography process
  ...rated circuit]] fabricated using a 7 nm process began in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it ...nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
  13 KB (1,941 words) - 02:40, 5 November 2022
• 5 nm lithography process
  The '''5 nanometer (5 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process ...nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
  11 KB (1,662 words) - 02:58, 2 October 2022
• 250 nm lithography process
  ...nometer (250 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[350 nm lithography process|350 nm pro ...et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
  6 KB (661 words) - 16:18, 21 August 2022
• 350 nm lithography process
  ...ography process''' (350 nm or 0.35 µm) is a [[technology node|full node]] semiconductor manufacturing process following the [[500 nm lithography process|500 nm pro
  5 KB (586 words) - 22:44, 4 April 2022
• 500 nm lithography process
  ...nometer (500 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[600 nm lithography process|600 nm pro ...pan="2" | [[TI]] || colspan="2" | [[Motorola]] || colspan="2" | [[National Semiconductor|National]] (BiCMOS)
  4 KB (438 words) - 06:15, 20 July 2018
• 1.2 µm lithography process
  ...aphy process''' was the semiconductor process technology used by the major semiconductor companies between in the late 1980s. 1 µm was phased out in the early 1990
  962 bytes (118 words) - 23:04, 20 May 2018
• 1.3 µm lithography process
  ...aphy process''' was the semiconductor process technology used by the major semiconductor companies between in the late 1980s. 1.3 µm was phased out from the late 1 * Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 International. IEEE, 1984.
  1 KB (138 words) - 12:57, 23 October 2022
• 110 nm lithography process
  ...10 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[130 nm lithography pr
  1 KB (143 words) - 05:57, 20 July 2018
• 150 nm lithography process
  ...ed circuit]] manufacturing using 150 nm process began in early 2000s. This technology superseded by commercial [[130 nm]], [[110 nm]], and [[90 nm]] processes.
  2 KB (238 words) - 02:56, 27 September 2020
• 7 µm lithography process
  ...thography process''' was the semiconductor process technology used by some semiconductor companies during the early to mid 1970s. This process was later superseded |Technology
  710 bytes (91 words) - 06:15, 18 January 2022

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