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Zen 5 - Microarchitectures - AMD
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Zen 5 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Introduction2024
Process4 nm, 3 nm
Core Configs192, 160, 144, 128, 96, 64, 48, 32, 24, 20, 16, 12, 10, 8, 6
PE Configs384, 320, 288, 256, 192, 128, 96, 64, 48, 40, 32, 24, 20, 16, 12
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAAMD64, x86-64
ExtensionsAMX, AVX, AVX2, AVX-512
Cores
Core NamesTurin,
Shimada Peak,
Granite Ridge,
Fire Range,
Strix Point
Succession

Zen 5 is a microarchitecture Already released and sold being by AMD as a successor to Zen 4

History

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 [1]

Codenames

Product Codenames:

Core Model C/T Target
Turin EPYC 9005 Up to 128/256 High-end EPYC 5th Gen series server multiprocessors
Turin Dense EPYC 9005 Up to 192/384 High-performance EPYC server processors
Shimada Peak Ryzen 9000 Up to 32/64 ? Threadripper Workstation & enthusiasts market processors
Granite Ridge Ryzen 9000 Up to 16/32 Mainstream to high-end desktops & PC market processors
(Gaming Desktop CPU)
Fire Range Ryzen 9000 Up to 16/32 Mainstream desktop & mobile processors
Strix Point Ryzen AI 300 Up to 12/24 Mainstream mobile processors with GPU
(Gaming APU with RDNA3 or RDNA4)
Strix Halo Ryzen AI 300 Up to 16/32 High-performance ultrathin notebook processors
Krackan Point Ryzen AI 300 Up to ?/? High-performance ultrathin mobile processors
Sonoma Valley Ryzen APU Family Up to ?/? AMD Low-end Ryzen APU Family, Samsung 4 nm (TSMC)
(Zen 5c Quad-core CPU, RDNA3 2CU GPU, TDP 35W)

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server

processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").

Architectural Codenames:

Arch Codename
Core Nirvana
CCD Eldora
Comparison
Core Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Zen 4c Zen 5 Zen 5c Zen 6 Zen 6c
Codename Core Valhalla Cerberus Persephone Dionysus Nirvana Prometheus Morpheus Monarch
CCD Aspen
Highlands 		Breckenridge Durango Vindhya Eldora
Cores
(threads) 		CCD 8 (16) 8 (16) 16 (32)
CCX 8 (16) 8 (16) 8 (16)
L3 cache CCD 32 MB 32 MB 32 MB 32 MB
CCX 32 MB 32 MB 16 MB 32 MB
Die size CCD area 44 mm2 66.3 mm2 72.7 mm2 70.6 mm2
Core area
(Fab node) 		7 mm2
(14 nm) 		(12 nm) (7 nm) (7 nm) (7 nm) 3.84 mm2
(5 nm) 		2.48 mm2
(5 nm) 		(4 nm) (3 nm) (2 nm) (2 nm)

Process Technology

Zen 5 is to be produced on a 4 nm process, Zen 5c is to be produced on a 3 nm process.

Architecture

AMD Zen 5 released in July 2024. The seventh microarchitecture in the Zen microarchitecture series.

Codenamed Granite Ridge, Strix Point, and Turin, it is slated for TSMC 4 nm or 3 nm manufacturing.
  • LITTLE design
- Improved 16% IPC and clock speed
- possibly more L3 cache per chiplet

Key changes from Zen 4

Core level (vs. Zen 4 microarchitectures)
  • Instruction set
AVX-512 VP2INTERSECT support
AVX-VNNI support
  • Front end
• Branch prediction improvements
- L1 BTB size increased significantly from 1.5K → 16K (10.7x)
- L2 BTB size increases from 7K → 8K
- Increased size of TAGE
- Introduction of 2-ahead predictor structure
- Return stack size increased from 32 → 52 entries (+62.5%)
• Improved instruction cache latency and bandwidth
- Instruction fetch bandwidth increased from 32B → 64B per cycle
- L2 instruction TLB size increased from 512 → 2048 entries (4x)
• Introducing a dual decode pipeline
- Decoder throughput scaled from 4 to 8 (2x4) per cycle (4 per thread, 4 in single thread)
- Op cache throughput expanded from 9 → 12 (2x6) per cycle (6 per thread, 6 for single thread)
- Unlike Intel E-Core, where a single thread can utilize multiple clusters, one cluster is used per SMT thread.
  • Back end
• Dispatch width of integer operations expanded from 6 → 8
• The size of ROB (reorder buffer) has been expanded from 320 to 448 entries (+40%)
• Integer register file capacity expanded from 192 → 240 entries (+25%)
• Floating point register file capacity expanded from 192 to 384 entries (2x)
• Flag register file capacity expanded to 192 entries
• Increased size of integer scheduler
- Scheduler size expanded from 4x24 (=96) → 88+56 (=144) entries (+50%)
- Adoption of integrated scheduler configuration similar to Intel P-Core
• Increased size of floating point scheduler
- The size of the pre-scheduler queue has been expanded from 64 to 96 entries (+50%).
- Scheduler size expanded from 2x32 (=64) → 3x38 (=114) entries (+78%)
• Number of ALUs increased from 4 → 6 (+50%)
• Number of multiplication units increases from 1 → 3 (3x)
• Number of branch units increased from 2 → 3 (+50%)
• Number of AGU increased from 3 → 4 (+33%)
- Number of loads that can be processed per cycle increased from 3 → 4 (same as 2 for 128 bits or more)
- Number of 128/256 bit stores that can be processed per cycle increased from 1 → 2
Desktop and server products such as Granite Ridge can process AVX-512 SIMD in one cycle.
However, mobile products process 256 bits in two cycles like the previous Zen 4.
  • Memory subsystem
• Load/Store Queue
- Increased size
• Prefetcher
- Added 2D stride prefetcher
- Improved stream & region prefetcher
• L1 data cache
- Capacity increased from 32 KB → 48 KB
- Associativity increases from 8-way → 12-way
- Bandwidth doubled
• L2 data cache
- Associativity increases from 8-way → 16-way
- Bandwidth increases from 32B → 64B per cycle
• L3 data cache
- Slight improvement in latency
- Maximum number of in-flight misses increased to 320
  • Physical design
Improved power gating technology
  • The overall expansion of the architecture has improved performance per clock
by an average of 16% compared to the previous generation.

Members

9005 Series (Zen 5)

See also: Turin and Zen 5 µarch


The fifth generation of EPYC processors was launched on October 10, 2024, at AMD's Advancing AI event, with general availability beginning in November 2024. Based on the Zen 5 microarchitecture, the 9005 series, codenamed "Turin", is manufactured by TSMC using a 4 nm process for standard Zen 5 cores and a 3 nm process for Zen 5c cores.

It utilizes the Socket SP5 socket, maintaining compatibility with the previous generation. The series offers core counts ranging from 8 cores to 192 cores, with support for up to 12 channels of DDR5-6000 memory (up to 6 TiB per socket) and 128 PCIe 5.0 lanes, enhancing performance and efficiency for high-performance computing, cloud, and AI workloads.

The series includes standard Zen 5 models, high-frequency "F" SKUs, single-socket "P" SKUs, and dense Zen 5c models, with TDPs ranging from 155 W to 500 W.

 List of Zen 5-based EPYC Processors
 Main SpecsFrequency
ModelPriceLaunchedCoresThreadsL2$L3$TDPMemoryBase FreqMax Boost
 Uniprocessors
EPYC 9015P$ 527November 20248168 MiB32 MiB155 WDDR5-60003.8 GHz4.1 GHz
EPYC 9125P$ 1,121November 2024163216 MiB64 MiB200 WDDR5-60004.0 GHz4.3 GHz
EPYC 9355P$ 4,771November 2024326432 MiB256 MiB300 WDDR5-60003.65 GHz4.05 GHz
EPYC 9755P$ 12,984November 2024128256128 MiB256 MiB400 WDDR5-60002.7 GHz4.1 GHz
 Multiprocessors (dual-socket)
EPYC 9015$ 527November 20248168 MiB32 MiB155 WDDR5-60003.8 GHz4.1 GHz
EPYC 9115$ 744November 2024122412 MiB32 MiB155 WDDR5-60003.6 GHz4.0 GHz
EPYC 9125$ 1,121November 2024163216 MiB64 MiB200 WDDR5-60004.0 GHz4.3 GHz
EPYC 9175F$ 2,624November 2024163216 MiB512 MiB320 WDDR5-60004.2 GHz5.0 GHz
EPYC 9215$ 1,518November 2024204020 MiB64 MiB200 WDDR5-60003.7 GHz4.1 GHz
EPYC 9255$ 2,238November 2024244824 MiB96 MiB240 WDDR5-60003.65 GHz4.05 GHz
EPYC 9275F$ 3,224November 2024244824 MiB96 MiB300 WDDR5-60004.1 GHz4.8 GHz
EPYC 9335$ 2,991November 2024326432 MiB128 MiB240 WDDR5-60003.35 GHz3.9 GHz
EPYC 9355$ 4,771November 2024326432 MiB256 MiB300 WDDR5-60003.65 GHz4.05 GHz
EPYC 9375F$ 5,198November 2024326432 MiB256 MiB320 WDDR5-60004.0 GHz4.8 GHz
EPYC 9455$ 5,987November 2024489648 MiB256 MiB300 WDDR5-60003.25 GHz3.85 GHz
EPYC 9535$ 6,876November 20246412864 MiB256 MiB300 WDDR5-60002.9 GHz3.75 GHz
EPYC 9555$ 9,251November 20246412864 MiB256 MiB360 WDDR5-60003.2 GHz4.0 GHz
EPYC 9575F$ 10,166November 20246412864 MiB256 MiB400 WDDR5-60003.5 GHz5.0 GHz
EPYC 9655$ 10,592November 20249619296 MiB256 MiB400 WDDR5-60002.7 GHz4.1 GHz
EPYC 9745$ 11,494November 2024128256128 MiB256 MiB400 WDDR5-60002.4 GHz3.8 GHz
EPYC 9755$ 12,984November 2024128256128 MiB256 MiB400 WDDR5-60002.7 GHz4.1 GHz
EPYC 9565$ 12,593November 20249619296 MiB384 MiB400 WDDR5-60002.8 GHz4.0 GHz
EPYC 9665$ 13,630November 20249619296 MiB384 MiB400 WDDR5-60003.0 GHz4.2 GHz
EPYC 9755F$ 13,999November 2024128256128 MiB256 MiB500 WDDR5-60003.1 GHz4.4 GHz
EPYC 9825$ 13,999November 2024144288144 MiB384 MiB400 WDDR5-60002.6 GHz3.9 GHz
EPYC 9845$ 14,399November 2024160320160 MiB384 MiB400 WDDR5-60002.4 GHz3.7 GHz
EPYC 9965$ 14,813November 2024192384192 MiB384 MiB500 WDDR5-60002.25 GHz3.7 GHz
 Frequency-optimized SKUs
EPYC 9175F$ 2,624November 2024163216 MiB512 MiB320 WDDR5-60004.2 GHz5.0 GHz
EPYC 9275F$ 3,224November 2024244824 MiB96 MiB300 WDDR5-60004.1 GHz4.8 GHz
EPYC 9375F$ 5,198November 2024326432 MiB256 MiB320 WDDR5-60004.0 GHz4.8 GHz
EPYC 9575F$ 10,166November 20246412864 MiB256 MiB400 WDDR5-60003.5 GHz5.0 GHz
EPYC 9755F$ 13,999November 2024128256128 MiB256 MiB500 WDDR5-60003.1 GHz4.4 GHz
Count: 0
32 :

Designers

  • David Suggs, chief architect

Bibliography

  1. ↑ Ryzen Processors: One Year Later

See also

AMD • Zen • Ryzen • EPYC
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Facts about "Zen 5 - Microarchitectures - AMD"
RDF feed
codenameZen 5 +
core count192 +, 160 +, 144 +, 128 +, 96 +, 64 +, 48 +, 32 +, 24 +, 20 +, 16 +, 12 +, 10 +, 8 + and 6 +
designerAMD +
first launched2024 +
full page nameamd/microarchitectures/zen 5 +
instance ofmicroarchitecture +
instruction set architectureAMD64 + and x86-64 +
manufacturerTSMC +
microarchitecture typeCPU +
nameZen 5 +
process4 nm (0.004 μm, 4.0e-6 mm) + and 3 nm (0.003 μm, 3.0e-6 mm) +
processing element count384 +, 320 +, 288 +, 256 +, 192 +, 128 +, 96 +, 64 +, 48 +, 40 +, 32 +, 24 +, 20 +, 16 + and 12 +