Revision as of 20:22, 22 June 2017

Skylake (SKL) is Intel's successor to Broadwell, a 14 nm process microarchitecture for mainstream desktops, servers, and mobile devices. Skylake succeeded the short-lived Broadwell which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel.

For desktop and mobile, Skylake is branded as 6th Generation Intel Core i3, Core i5, Core i7, and Core i9 processors. For workstations it's branded as Xeon E3 v5 For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.

Codenames

Release Dates

Skylake was first demonstrated at the 2014 Intel Developer Forum in San Francisco on September 9 with the goals of launching in the second half of 2015.

Process Technology

Main article: Broadwell § Process Technology

Skylake uses the same 14 nm process used for the Broadwell microarchitecture for all mainstream consumer parts (Core, Celeron, et al). Unlike mainstream Skylake models, the enthusiasts (Skylake X) models are fabricated on Intel's enhanced 14+ nm process which is used by Kaby Lake (see Kaby Lake § Process Technology for more info).

Compatibility

Compiler support

Architecture

Overall Skylake builds upon Intel's previous microarchitecture, Broadwell, but includes a wider and more beefed up front end, more optimized execution engine, and numerous other enhancements. Intel designed Skylake to encompass a wide range of devices and applications with a large emphasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.

Key changes from Broadwell

• 8x performance/watt over Nehalem (Up from 3.5x in Haswell)
• Mainstream chipset
  • Lynx Point → Sunrise Point
  • Bus/Interface to Chipset
    • DMI 3.0 (from 2.0)
      • Skylake S and Skylake H cores, connected by 4-lane DMI 3.0
      • Skylake Y and Skylake U cores have chipset in the same package (simplified OPIO)
      • Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane
      • Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
  • PCIe & DMI upgraded to Gen3
  • More I/O (configurable as PCIe/SATA/USB3)
  • Lower-power I/O (eMMC, UFS, SDXC)
  • CSI-2 for the integrated IPU (mobile SKUs)
  • Intel Sensor Solution Hub integration
• System Agent
  • New Image Processing Unit (IPU)
    • Incorporates an image signal processor (ISP)
    • Mobile client models only
  • Can now have its own variable voltage and frequency
• Core
  • Front End
    • Larger legacy pipeline delivery (5 µOPs, up from 4)
      • Another simple decoder has been added.
    • Allocation Queue (IDQ)
      • Larger delivery (6 µOPs, up from 4)
      • 2.28x larger buffer (64/thread, up from 56)
      • Partitioned for each active threads (from unified)
    • Improved branch prediction unit
      • reduced penalty for wrong direct jump target
      • No specifics were disclosed
    • µOP Cache
      • instruction window is now 64 Bytes (from 32)
      • 1.5x bandwidth (6 µOPs/cycle, up from 4)
  • Execution Engine
    • Larger re-order buffer (224 entries, up from 192)
    • Larger scheduler (97 entries, up from 64)
      • Larger Integer Register File (180 entries, up from 168)
      • Larger Retire (4 µOPs/cycle/thread, up from 4 µOPs/cycle/core)?
  • Memory Subsystem
    • Larger store buffer (56 entries, up from 42)
    • L2$ was changed from 8-way to 4-way set associative
    • Page split load penalty reduced 20-fold
    • Larger Write-back buffer
    • Larger Line Fill Buffer?

• Memory
  • Support for faster DDR-2400 memory
  • L3$ re-gained 512 KiB/core (See §eDRAM architectural changes for the reason)
  • A new coherent cache fabric implementation
    • doubles the throughput of the last level cache (LLC, L3$ in this case) miss handling
    • 50% improvement in bandwidth/watt
    • new eDRAM cache architecture for higher bandwidth
• TLBs
  • ITLB
    • 4 KiB page translations was changed from 4-way to 8-way associative
  • STLB
    • 4 KiB + 2 MiB page translations was changed from 6-way to 12-way associative
• Electrical
  • The fully integrated voltage regulator (FIVR) is moved back to the motherboard
    • Originally intended to be a cost-cutting measure by moving the FIVR on-die as well as making it more efficient, the move resulted in unintentionally making the FIVR the limiting factor when it came to overclocking.
  • DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals)
• Testability
  • New support for Direct Connect Interface (DCI), a new debugging transport protocol designed to allow debugging of closed cases (e.g. laptops, embedded) by accessing things such as JTAG through any USB 3 port.

Server

Unlike client models, Skylake servers and HEDT models will still incorporate the fully integrated voltage regulator (FIVR) on-die. Those chips also have an entirely new multi-core architecture along with a new mesh topology interconnect network (from ring topology).

• Memory
  • L2$
    • Increased to 1 MiB/core (from 250 KiB/core)
  • L3$
    • Was made non-inclusive (from inclusive)
    • Reduced to 1.375 MiB/core (from 2.5 MiB/core)

CPU changes

• Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).
• MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.
• ADC and SBB have throughput of 1 op/cycle, same as Haswell.
• Vector moves have throughput of 4 op/cycle (move elimination).
• Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.
• Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.
• Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.
• Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.
• Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.
• Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle.
• vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op.
• Throughput of some MMX ALU ops (such as PAND mm1, mm2) is decreased to 2 or 1 op/cycle (users are expected to use wider SSE/AVX registers instead).

New GPU Features & Changes

• Adaptive scalable texture compression (ASTC)
• 16x multi-sample anti-aliasing (MSAA)
• Post depth test coverage mask
• Floating point atomics (min/max/cmpexch)
• Min/max texture filtering
• Multi-plane overlays

Graphics

• Improved underlying implementation of the memory QoS for higher resolution displays and the integrated image signal processor (ISP)
  • Allow for higher concurrent bandwidth
• Skylake retires VGA support, multi-monitor support for up to 3 displays via HDMI 1.4, DP 1.2, and eDP 1.3 interfaces.
• Direct X 12
• OpenCL 2.0
• OpenGL 4.4
• Up to 24 EUs GT2 (same as Haswell); 48 EUs for GT3, and up to 72 EUs on Iris Pro Graphics
  • 1,152 GFLOPS

IGP	Execution Units	GT	eDRAM	Series (Y/U/H/S)
HD Graphics	12	2+1	-	Y
HD Graphics 510	12	2+2	-	U/S
HD Graphics 515	24	2+2	-	Y
HD Graphics 520	24	4+2 2+2	-	U
HD Graphics 530	24	4+2 2+2	-	H/S
HD Graphics P530	24	4+2	-	H
Iris Graphics 540	48	2+3e	64 MiB	U
Iris Graphics 550	48	2+3e	64 MiB	U
Iris Pro Graphics 580	72	4+4e	128 MiB	H

New instructions

Main article: See §Added instructions for the complete list

Skylake introduced a number of new instructions:

• SGX - Software Guard Extensions
• MPX -Memory Protection Extensions
• AVX-512 - Advanced Vector Extensions 512 (Only on high-end Xeon models (SKX))

Block Diagram

Client SoC

Entire SoC Overview (dual)

Entire SoC Overview (quad)

Individual Core

Gen9

See Gen9#Gen9.

Server MPUs

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Intel has not disclosed the details of the Skylake server configuration.

Memory Hierarchy

Client

Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to Broadwell/Haswell.

• Cache
  • L0 µOP cache:
    • 1,536 µOPs, 8-way set associative
      • 32 sets, 6-µOP line size
      • statically divided between threads, per core, inclusive with L1I
  • L1I Cache:
    • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB, 8-way set associative
    • 64 sets, 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use (simple pointer accesses)
      • 5 cycles for complex addresses
    • 64 B/cycle load bandwidth
    • 32 B/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • Unified, 256 KiB, 4-way set associative
    • 1024 sets, 64 B line size
    • Non-inclusive
    • 12 cycles for fastest load-to-use
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache/LLC:
    • Up to 2 MiB Per core, shared across all cores
    • Up to 16-way set associative
    • Inclusive
    • 64 B line size
    • Write-back policy
    • Per each core:
      • Read: 32 B/cycle (@ ring clock)
      • Write: 32 B/cycle (@ ring clock)
    • 42 cycles for fastest load-to-use
  • Side Cache:
    • 64 MiB & 128 MiB eDRAM
    • Per package
    • Only on the Iris Pro GPUs
    • Read: 32 B/cycle (@ eDRAM clock)
    • Write: 32 B/cycle (@ eDRAM clock)
  • System DRAM:
    • 2 Channels
    • 8 B/cycle/channel (@ memory clock)
    • 42 cycles + 51 ns latency

Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partitioning
    • 2 MiB / 4 MiB page translations:
      • 8 entries per thread; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; fully associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

Server

The memory hierarchy for Skylake's server and HEDT processors has been rebalanced. Note that the L3 is now non-inclusive and some of the SRAM from the L3 cache was moved into the private L2 cache.

• • L2 Cache:
    • Unified, 1 MiB, 8-way set associative
    • Non-inclusive
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache:
    • 1.375 MiB/s, shared across all cores
    • 11-way set associative
    • Non-Inclusive
    • 64 B line size
    • Write-back policy

Overview

Skylake inherits much of the Core design philosophy which was enhanced significantly over the past number of architectures. Skylake, like its predecessor Broadwell, is also a dual-threaded and complex out-of-order pipeline. Skylake which builds on Broadwell incorporates large number of enhancements that has improved performance and efficiency in order to cover a large spectrum of devices from ultra-low power to high-performance computing. Additionally, a large number of improvements were done to the integrated graphics and multimedia capabilities as well as a new set of security technologies were introduced.

Design goals & new goals

Skylake tries to address 4 major design goals: Scalability, Performance, Power, and Media & Graphics. Skylake started out as a "traditional client product" when initial design goals and development started back in 2010. At that time, Skylake was expected to cover products ranging from thin-and-lights all the way up to desktops. This translated to roughly 3x TDP scale and 2x form factor between the smallest and biggest models. With the introduction of Ultralight, Skylake design goals were extended to a new class of smaller form factors (down to 15 W). Skylake design goals were later further extended to more mobility segments and even smaller form factors. The final end result is a microarchitecture that now spans 20-fold TDP scale (from 3.5 W all the way to 80 W+) and up to 4-fold form factor between the lowest power model and the highest performance model. Intel claims that Skylake also succeeded in reducing power by 40-60% during important workloads such as video, graphics, and idle power which especially affect models where battery life is absolutely critical.

It's interesting to note that Skylake's end result managed to overlap and to some degree exceed Intel's own ultra-low power (ULP) series of microarchitectures (i.e. Silvermont and Goldmont).

Product Development Vectors:

• Form factor reduction - Emphasis was placed on reduction of form factor which includes both actual die size and package size.
• Platform minimization - Effort was spent on reducing the overall platform size include reduction of system board size, components, and power.
• Better life scenario power reduction - (mobile segment) The reduction of power during critical workloads such as video playback, video conferencing, and various other multimedia applications where the CPU itself is mostly idle.
• IA performance - Improvements to both power and performance of the CPU core
• IGP performance - Improvement to both power and performance of the GPU
• New Security technology - Better protection against hardware and software attacks

SoC design

The Skylake system on a chip consists of a five major components: CPU core, LLC, Ring interconnect, System agent, and the integrated graphics. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. superset of features). Skylake features an improved core (see § Pipeline) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically dual-core while mainstream desktop models are typically quad-core with dual-core desktop models still offered for value models (e.g. Celeron). Accompanying the cores is the LCC (last level cache or L3$ as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth.

Accompanying the cores is the Gen9 integrated graphics unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 (Gen9 § Pipeline) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated eDRAM ranging from 64 GiB to 120 GiB in capacity. The eDRAM is packaged along with the SoC in the same package.

On the other side is the System Agent (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded integrated memory controller (IMC) with most mainstream models supporting faster memory and dual-channel DDR4. The SA in Skylake also includes the Display Controller which now supports higher resolution displays with up to three displays for all mainstream models.

The SA also incorporates up to 20 lanes of PCIe with lesser amounts depending on the model. Of the 20 lanes, x16 PCIe lanes are offered for an external dedicated graphics hookup with the other four lanes reserved for communication with the southbridge chipset over Intel's new proprietary DMI 3.0 bus. The upgrade from DMI 2.0 (used in previous architectures) to 3.0 increased the bandwidth by 60% (8.0 GT/s from 5). For some models where form factor is exceptionally critical, such as those used for ultralight device, the chipset is packaged along with the SoC utilizing an on-package-interconnect (OPI) instead.

The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an image signal processor (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer.

Core (Client)

Overview

Skylake shares most of the development vectors with its predecessor while introducing a one of new constraint. The overall goals were:

• Performance improvements - the traditional way of milking more performance by increasing the instructions per cycle as well as clock frequency.
• Power efficiency - reduction of power for all functional blocks
• Security enhancements - new security features are implemented in hardware in the core
• Configurability

Configurability

Intel has been experiencing a growing divergence in functionality over the last number of iterations of their microarchitecture between their mainstream consumer products and their high-end HPC/server models. Traditionally, Intel has been using the same exact core design for everything from their lowest end value models (e.g. Celeron) all the way up to the highest-performance enterprise models (e.g. Xeon E7). While the two have fundamentally different chip architectures, they use the same exact CPU core architecture as the building block.

This design philosophy has changed with Skylake. In order to better accommodate the different functionalities of each segment without sacrificing features or making unnecessary compromises Intel went with a configurable core. The Skylake core is a single development project, making up a master superset core. The project result in two derivatives: one for servers and one for clients. All mainstream models (from Celeron/Pentium all the way up to Core i7/Xeon E3) use the client core configuration. Server models (e.g. Xeon E5/Xeon E7) will be using the new server configuration.

The exact server core details have not been disclosed yet, however it's expected to feature Advanced Vector Extensions 512 (AVX-512).

Pipeline

The Skylake core focuses on extracting performance and reducing power through a number of key ways. Intel builds Skylake on previous microarchitectures, descendants of Sandy Bridge. For the core to increase the overall performance, Intel focused on extracting additional parallelism.

Broad Overview

At a 5,000 foot view, Skylake represents the logical evolution from Haswell and Broadwell. Therefore, despite some significant differences from the previous microarchitecture, the overall designs is fundamentally the same and can be seen as enhancements over Broadwell rather than a complete change.

The pipeline can be broken down into three areas: the front-end, back-end or execution engine, and the memory subsystem. The goal of the front-end is to feed the back-end with a sufficient stream of operations which it gets by decoding instructions coming from memory. The front-end has two major pathways: the µOPs cache path and the legacy path. The legacy path is the traditional path whereby variable-length x86 instructions are fetched from the level 1 instruction cache, queued, and consequently get decoded into simpler, fixed-length µOPs. The alternative and much more desired path is the µOPs cache path whereby a cache containing already decoded µOPs receives a hit allowing the µOPs to be sent directly to the decode queue.

Regardless of which path an instruction ends up taking it will eventually arrive at the decode queue. The IDQ represents the end of the front-end and the in-order part of the machine and the start of the execution engine which operates out-of-order.

In the back-end, the micro-operations visit the reorder buffer. It's there where register allocation, renaming, and retiring takes place. At this stage a number of other optimizations are also done. From the reorder buffer, µOPs are sent to the unified scheduler. The scheduler has a number of exit ports, each wired to a set of different execution units. Some units can perform basic ALU operations, others can do multiplication and division, with some units capable of more complex operations such as various vector operations. The scheduler is effectively in charge of queuing the µOPs on the appropriate port so they can be executed by the appropriate unit.

Some µOPs deal with memory access (e.g. load & store). Those will be sent on dedicated scheduler ports that can perform those memory operations. Store operations go to the store buffer which is also capable of performing forwarding when needed. Likewise, Load operations come from the load buffer. Skylake features a dedicated 32 KiB level 1 data cache and a dedicated 32 KiB level 1 instruction cache. It also features a core-private 256 KiB L2 cache that is shared by both of the L1 caches.

Each core enjoys a slice of a third level of cache that is shared by all the core. In the client configuration for Skylake, there are either two cores or four cores connected while in the server configuration, up to 28 cores may be hooked together on a single chip.

Front-end

The front-end is is tasked with the challenge of fetching the complex x86 instructions from memory, decoding them, and delivering them to the execution units. In other words, the front end needs to be able to consistently deliver enough µOPs from the instruction code stream to keep the back-end busy. When the back-end is not being fully utilized, the core is not reaching its full performance. A poorly or under-performing front-end will translate directly to a poorly performing core. This challenge is further complicated by various redirection such as branches and the complex nature of the x86 instructions themselves.

Fetch & pre-decoding

On their first pass, instructions should have already been prefetched from the L2 cache and into the L1 cache. The L1 is a 32 KiB, 8-way set associative cache, identical in size and organization to previous generations. Skylake fetching is done on a 16-byte fetch window. A window size that has not changed in a number of generations. Up to 16 bytes of code can be fetched each cycle. At this point they are still macro-ops (i.e. variable-length x86 architectural instruction). Instructions are brought into the pre-decode buffer for initial preparation.

x86 instructions are complex, variable length, have inconsistent encoding, and may contain multiple operations. At the pre-decode buffer the instructions boundaries get detected and marked. This is a fairly difficult task because each instruction can vary from a single byte all the way up to fifteen. Moreover, determining the length requires inspecting a couple of bytes of the instruction. In addition boundary marking, prefixes are also decoded and checked for various properties such as branches. As with previous microarchitectures, the pre-decoder has a throughput of 6 macro-ops per cycle or until all 16 bytes are consumed, whichever happens first. Note that the predecoder will not load a new 16-byte block until the previous block has been fully exhausted. For example, suppose a new chunk was loaded, resulting in 7 instructions. In the first cycle, 6 instructions will be processed and a whole second cycle will be wasted for that last instruction. This will produce the much lower throughput of 3.5 instructions per cycle which is considerably less than optimal. Likewise, if the 16-byte block resulted in just 4 instructions with 1 byte of the 5th instruction received, the first 4 instructions will be processed in the first cycle and a second cycle will be required for the last instruction. This will produce an average throughput of 2.5 instructions per cycle. Note that there is a special case for length-changing prefix (LCPs) which will incur additional pre-decoding costs. Real code is often less than 4 bytes which usually results in a good rate.

All of this works along with the branch prediction unit which attempts to guess the flow of instructions. In Skylake, the branch predictor has also been improved. The branch predictor now has reduced penalty (i.e. lower latency) for wrong direct jump target prediction. Additionally, the predictor in Skylake can inspect further in the byte stream than in previous architectures. The intimate improvements done in the branch predictor were not further disclosed by Intel.

Instruction Queue & MOP-Fusion

cmp eax, [mem]
jne loop

cmpjne eax, [mem], loop

See also: Macro-Operation Fusion

The pre-decoded instructions are delivered to the Instruction Queue (IQ). In Broadwell, the Instruction Queue has been increased to 25 entries duplicated over for each thread (i.e. 50 total entries). It's unclear if that has changed with Skylake. One key optimization the instruction queue does is macro-op fusion. Skylake can fuse two macro-ops into a single complex one in a number of cases. In cases where a test or compare instruction with a subsequent conditional jump is detected, it will be converted into a single compare-and-branch instruction. Those fused instructions remain fused throughout the entire pipeline and get executed as a single operation by the branch unit thereby saving bandwidth everywhere. Only one such fusion can be performed each cycle.

Decoding

Up to five pre-decoded instructions are sent to the decoders each cycle. Decoders read in macro-operations and emit regular, fixed length µOPs. Skylake represents a big genealogical change from the last couple of microarchitectures. Skylake's pipeline is wider than it predecessors; Skylake adds another simple decoder. The five decoders are asymmetric; the first one, Decoder 0, is a complex decoder while the other four are simple decoders. A simple decoder is capable of translating instructions that emit a single fused-µOP. By contrast, a complex decoder can decode anywhere from one to four fused-µOPs. Skylake is now capable of decoding 5 macro-ops per cycle or 25% more than Broadwell, however this does not translates directly to direct IPC uplift to due to various other more restricting points in the pipeline. Intel chose not increase the number of complex decoders because it's much harder to extract additional parallelism from the µOPs emitted by a complex instruction. Overall up to 5 simple instructions can be decoded each cycle with lesser amounts if the complex decoder needs to emit addition µOPs; i.e., for each additional µOP the complex decoder needs to emit, 1 less simple decoder can operate. In other words, for each additional µOP the complex decoder emits, one less decoder is active.

MSROM & Stack Engine

There are more complex instructions that are not trivial to be decoded even by complex decoder. For instructions that transform into more than four µOPs, the instruction detours through the microcode sequencer (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode sequencer is done. During that time, the decoders are disabled.

x86 has dedicated stack machine operations. Instructions such as PUSH, POP, as well as CALL, and RET all operate on the stack pointer (ESP). Without any specialized hardware, such operations would would need to be sent to the back-end for execution using the general purpose ALUs, using up some of the bandwidth and utilizing scheduler and execution units resources. Since Pentium M, Intel has been making use of a Stack Engine. The Stack Engine has a set of three dedicated adders it uses to perform and eliminate the stack-updating µOPs (i.e. capable of handling three additions per cycle). Instruction such as PUSH are translated into a store and a subtraction of 4 from ESP. The subtraction in this case will be done by the Stack Engine. The Stack Engine sits after the decoders and monitors the µOPs stream as it passes by. Incoming stack-modifying operations are caught by the Stack Engine. This operation alleviate the burden of the pipeline from stack pointer-modifying µOPs. In other words, it's cheaper and faster to calculate stack pointer targets at the Stack Engine than it is to send those operations down the pipeline to be done by the execution units (i.e., general purpose ALUs).

µOP cache & x86 tax

Decoding the variable-length, inconsistent, and complex x86 instructions is a nontrivial task. It's also expensive in terms of performance and power. Therefore, the best way for the pipeline to avoid those things is to simply not decode the instructions. This is the job of the µOP cache or the Decoded Stream Buffer (DSB). Skylake's µOP cache is organized similarly to previous generations like Sandy Bridge, however both the bandwidth and the tracking window was increased. The cache is organized into 32 sets of 8 cache lines with each line holding up to 6 µOP for a total of 1,536 µOPs. Whereas previously (e.g. Haswell) the µOP cache operated on 32-byte windows, in Skylake the window size has been doubled to 64-bytes. The micro-operation cache is competitively shared between the two threads and can also hold pointers to the microcode. The µOP cache has an average hit rate of 80%.

A hit in the µOP allows for up to 6 µOP (i.e., entire line) per cycle to be sent directly to the Instruction Decode Queue (IDQ), bypassing all the pre-decoding and decoding that would otherwise have to be done. Whereas the legacy decode path works in 16-byte instruction fetch windows, the µOP cache has no such restriction and can deliver 6 µOP/cycle corresponding to the much bigger 64-byte window. Previously (e.g., Broadwell), the bandwidth was lower at 4 µOP per cycle. The 1.5x bandwidth increase greatly improves the numbers of µOP that the back-end can take advantage of in the out-of-order part of the machine.

Allocation Queue

The emitted µOPs from the decoders are sent directly to the Allocation Queue (AQ) or Instruction Decode Queue (IDQ). The Allocation Queue acts as the interface between the front-end (in-order) and the back-end (out-of-order). Skylake's Allocation Queue has more than doubled from Broadwell from 28-entries per thread to 64-entries per thread. Unlike in Haswell, the IDQ is no longer competitively shared; it's partitioned between two active threads. The queue's purpose is effectively help absorb bubbles which may be introduced in the front-end, ensuring that a steady stream of 6 µOPs are delivered each cycle.

µOP-Fusion & LSD

The IDQ does a number of additional optimizations as it queues instructions. The Loop Stream Detector (LSD) is a mechanism inside the IDQ capable of detecting loops that fit in the IDQ and lock them down. That is, the LSD can stream the same sequence of µOPs directly from the IDQ continuously without any additional fetching, decoding, or utilizing additional caches or resources. Streaming continues indefinitely until reaching a branch mis-prediction. Note that while the LSD is active, the rest of the front-end is effectively disabled.

The LSD in Skylake can take advantage of the considerably larger IDQ; capable of detecting loops up to 64 µOPs per thread. The LSD is particularly excellent in for many common algorithms that are found in many programs (e.g., tight loops, intensive calc loops, searches, etc..).

Execution engine

Skylake's back-end or execution engine deals with the execution of out-of-order operations. Much of the design is inherited from previous architectures such as Haswell but has been widened to explorer more instruction-level parallelism opportunities. From the allocation queue instructions are sent to the Reorder Buffer (ROB) at the rate of up to 6 fused-µOPs each cycle. Skylake's throughput is up by 2 fused-µOPs per cycle from Broadwell in order to accommodate the wider front-end.

Renaming & Allocation

Like the front-end, the Reorder Buffer has been increased to 224 entries, 32 entries more than Broadwell. It is at this stage that architectural registers are mapped onto the underlying physical registers. Other additional bookkeeping tasks are also done at this point such as allocating resources for stores, loads, and determining all possible scheduler ports. Register renaming is also controlled by the Register Alias Table (RAT) which is used to mark where the data we depend on is coming from (after that value, too, came from an instruction that has previously been renamed). In previous microarchitectures, the RAT could handle 4 µOPs each cycle. Intel has not disclosed if that has changed in Skylake but it's possible. If this has not change, Skylake can rename any four registers per cycle. This includes the same register renamed four times in a single cycle. If the rename has not increased in Skylake, some aspects of improvements that were done in the prefetch/decode stages are effectively lost. Note that the ROB still operates on fused µOPs, therefore 4 µOPs can effectively be as high as 8 µOPs.

It should be noted that there is no special costs involved in splitting up fused µOPs before execution or retirement and the two fused µOPs only occupy a single entry in the ROB.

Since Skylake performs speculative execution, it can speculate incorrectly. When this happens, the architectural state is invalidated and as such needs to be rolled back to the last known valid state. Skylake has a 48-entry Branch Order Buffer (BOB) that keeps tracks of those states for this very purpose.

Optimizations

Skylake as a number of optimizations it performs prior to entering the out-of-order and renaming part. Three of those optimizations include Move Elimination and Zeroing Idioms, and Ones Idioms. A Move Elimination is capable of eliminating register-to-register moves (including chained moves) prior to bookkeeping at the ROB, allowing those µOPs to save resources and eliminating them entirely. Eliminated moves are zero latency and are entirely removed from the pipeline. This optimization does not always succeed; when it fails, the operands were simply not ready. On average this optimization is almost always successful (upward of 85% in most cases). Move elimination works on all 32- and 64-bit GP integer registers as well as all 128- and 256-bit vector registers.

xor eax, eax

There are some exceptions that Skylake will not optimize, most dealing with signedness. sign-extended moves cannot be eliminated and neither can zero-extended from 16-bit to 32/64 big registers (note that 8-bit to 32/64 works). Likewise, in the other direction, no moves to 8/16-bit registers can be eliminated. A move of a register to itself is never eliminated.

When instructions use registers that are independent of their prior values, another optimization opportunity can be exploited. A second common optimization performed in Skylake around the same time is Zeroing Idioms elimination. A number common zeroing idioms are recognized and consequently eliminated in much the same way as the move eliminations are performed. Skylake recognizes instructions such as XOR, PXOR, and XORPS as zeroing idioms when the source and destination operands are the same. Those optimizations are done at the same rate as renaming during renaming (at 4 µOPs per cycle) and the register is simply set to zero.

The ones idioms is another dependency breaking idiom that can be optimized. In all the various PCMPEQx instructions that perform packed comparison the same register with itself always set all bits to one. On those cases, while the µOP still has to be executed, the instructions may be scheduled as soon as possible because all the decencies are resolved.

Scheduler

The scheduler itself was increased by 50%; with up to 97 entries (from 64 in Broadwell) being competitively shared between the two threads. Skylake continues with a unified design; this is in contrast to designs such as AMD's Zen which uses a split design each one holding different types of µOPs. Scheduler includes the two register files for integers and vectors. It's in those register files that output operand data is store. In Skylake, the integer register file was also slightly increased from 160 entries to 180.

At this point µOPs are not longer fused and will be dispatched to the execution units independently. The scheduler holds the µOPs while they wait to be executed. A µOP could be waiting on an operand that has not arrived (e.g., fetched from memory or currently being calculated from another µOPs) or because the execution unit it needs is busy. Once the µOP is ready, they are dispatched through their designated port. The scheduler will send the oldest ready µOP to be executed on each of the eight ports each cycle.

The scheduler had its ports rearranged to better balance various instructions. For example, divide and sqrt instructions latency and throughput were improved. The latency and throughput of floating point ADD, MUL, and FMA were made uniformed at 4 cycles with a throughput of 2 µOPs/clock. Likewise the latency of AES instructions were significantly reduced from 7 cycles down to 4.

Scheduler Ports & Execution Units

Retirement

Once a µOP executes, or in the case of fused µOPs both µOPs have executed, they can be retired. Haswell is able to commit up to four fused µOPs each cycle; Skylake has likely increased this, possibly from 4 µOPs/cycle/core to up from 4 µOPs/cycle/thread(?). Retirement happens in-order and releases any used resources such as those used to keep track in the reorder buffer.

Memory subsystem

Skylake's memory subsystem is in charge of the loads and store requests and ordering. Since Haswell, it's possible to sustain two memory reads (on ports 2 and 3) and one memory write (on port 4) each cycle. Each memory operation can be of any register size up to 256 bits. Skylake memory subsystem has been improved. The store buffer has been increased by 14 entries from Broadwell to 56 for a total of 128 simultaneous memory operations in-flight or roughly 60% of all µOPs. Special care was taken to reduce the penalty for page-split loads; previously scenarios involving page-split loads were thought to be rarer than they actually are. This was addressed in Skylake with page-split loads are now made equal to other splits loads. Expect page split load penalty down to 5 cycles from 100 cycles in Broadwell. The average latency to forward a load to store has also been improved and stores that miss in the L1$ generate L2$ requests to the next level cache much earlier in Skylake than before.

The L2 to L1 bandwidth in Skylake is the same as Haswell at 64 bytes per cycle in either direction. Note that one operation can be done each cycle; i.e., the L1 can either receive data from the L1 or send data to the Load/Store buffers each cycle, but not both. Latency from L2$ to L3$ has also been increased from 4 cycles/line to 2 cycles/line. The bandwidth from the level 2 cache to the shared level 3 is 32 bytes per cycle.

eDRAM architectural changes

Intel ships a number of products with Embedded DRAM incorporated on package in order to increase performance of the integrated graphics and to a lesser degree the code through additional bandwidth and caching. There has been a number of significant architectural changes in how the eDRAM works in Skylake.

In Broadwell, the eDRAM was statically attached to the LLC (last level cache, L3$ from the perspective of the CPU Cores and L4$ from the perspective of the IGP), effectively stealing half a Mebibyte per core in the process, but behaving as an architectural true level 4 cache. This was fundamentally changed in Skylake. In Skylake, Intel removed the eDRAM from the LLC to its own array, re-freeing the 512 KiB (hence the 1.5 MiB/core in Broadwell and 2 MiB back in Skylake), but also removing the undesired dependency between the capacity of the eDRAM and the number of cores. Skylake's cache is effectively no longer a true level 4 cache but rather a memory side cache. This has a number of benefits such as that each and every memory access that goes through the memory controller gets looked up in the eDRAM. On a satisfied hit, the value is obtained from there. On a miss, a value gets allocated and stored in the eDRAM (subject to a number of restrictions, for example no I/O devices requests get cached on the eDRAM).

Skylake vs Broadwell eDRAM Architecture
Broadwell	Skylake

The new eDRAM changes mean it's no longer architectural - capable of caching any data (including "unreachable memory", display engines, and effectively any memory transfer not bound by software restrictions) and is entirely invisible to software (one exception noted later) in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performance, the graphics driver may decide to limit certain memory accesses to only the eDRAM, only the LLC, or in both of them.

Core (Server)

There are a number of major differences in the Skylake server configuration vs the client configuration.

Memory subsystem

The medium level cache (MLC) and last level cache (LLC) was rebalanced. Traditionally, Intel had a 256 KiB L2 cache which was duplicated along with the L1s over in the LLC which was 2.5 MiB. That is, prior to Skylake, the 256 KiB L2 cache actually took up 512 KiB of space. In Skylake Intel doubled the L2 and quadrupled the effective capacity to 1 MiB while decreasing the LLC to 1.375. The LLC is also now made non-inclusive, i.e., the L2 may or may not be in the L3 (no guarantee is made).

Having an inclusive L3 makes cache coherence considerably easier to implement. Snooping only requires checking the L3 cache tags to know if the data is on board and in which core. It also makes passing data around a bit more efficient. It's currently unknown what mechanism is being used to reduce snooping.

New Technologies

Software Guard Extension (SGX)

Main article: Intel's Software Guard Extension

Software Guard Extension (SGX) is a new inter-software guard x86 extension that allows software in user-level mode to create isolated secure environments called "enclaves" for storing data or code. Data and code stored in enclaves are protected from external processes including code executing with higher privileges including the operating system or a hypervisor (including all forms of debugging).

Memory Protection Extension (MPX)

Main article: Intel's Memory Protection Extension

Memory Protection Extension (MPX) is a new x86 extension that offers a hardware-level bound checking implementation. This extension allows an application to define memory boundaries for allocated memory areas. The processors can then check all proceeding memory accesses against those boundaries to ensure accesses are not out of bound. A program accessing a boundary-marked buffer out of buffer will generate an exception.

Power

"Speed Shift" (new power management)

Ever since the introduction of the modern power management unit on a microprocessor, it was effectively the role of the operating system to determine the desired operating frequency and voltage (i.e. a p-state) for the current workload. When the CPU utilization peaked, it was the role of the operating system to bump up the frequency to help cope with it. The issue has always been the limitation of the operating system. One such major limitation is the granularity of the operating system response time - usually in the 10s of milliseconds (anything lower than that would likely be too intensive and would not yield better result). A second major issue is that the operating system doesn't have an instantaneous observation of the microarchitectural behavior of the workload.

Intel introduced Speed Shift with Skylake, a new methodology for quickly alternating core frequencies in response to power loads. Intel introduced a new unit called Package Control Unit (PCU) which is effectively a full fledged microcontroller (containing power management logic and firmware) that collects and tracks many internal SoC statistics as well as external power telemetry (e.g. Psys and iMon). PCU is also capable of interfacing with the OS, BIOS, and DPTF. Speed Shift improves the performance of frequency shifting by off-loading the control from the operating system to the PCU.

Speed Shift effectively eliminates the need for the OS to manages the P-states - though it does have the final say (unless special exceptions occur such as thermal throttling). Intel calls this "autonomous P-state", allowing Speed Shift to kick in in a matter of just ~1 millisecond (whereas the operating system-based p-states control can be as slow as 30 ms). Speed Shift effectively reduces hitting peak frequency in around ~30 ms from over 100 ms (OS-based implementation as before). While Speed Shift is capable of full range shift by default, the operating system can set the minimum QoS, maximum frequency and power/performance hints when desired. The final result should be higher performance and specially higher responsiveness at power constrained form factors.

SpeedStep Technology Expansion

Main article: SpeedStep Technology

Prior to Skylake, SpeedStep had three major domains: Cores, Integrated Graphics, and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the System Agent, Memory, and the eDRAM I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains.

Information from the new domains, including additional thermal skin temperature control information is now supplied to OEMs.

Power of System (Psys)

Psys (Power of System) is a way for the PCU to monitor the performance and the total platform power provided to the chip. The chip uses a number of autonomous algorithms (one for "Low Range" and one for "High Range"). The Low Range algorithm frequency is lowered to conserve energy. Algorithm is capable of overriding the low P state - a state calculated ever millisecond based on the active workload and system characteristics. The High Range algorithm deals with elevating frequency for the benefit of increase performance (at the cost of increase energy/inefficiency). The exact ratio of ΔPower/ΔPerformance ≤ αPreference can be finely controlled via the OS and user preferences.

Other Power Optimization

Skylake includes a number of additional power optimization changes:

• AVX2 is now power gated - prior to Skylake, AVX2 was not power gated which meant it was susceptible to leakage. Starting with Skylake, those instruction are full power gated and turn off when not used.
• Many older/legacy underused resources have been downscaled.
• Various scenario-based power optimizations were done, including:
  • Idle power is reduced further
  • C1 state power reduction (improved dynamic capacitance C_dyn)
  • For specific tasks such as streaming, Skylake is capable of powering down certain components of the GPU maintaining power on to the critical components needed for that purpose.

Overall Skylake enjoys better performance/Watt per core for 8x performance/watt over Nehalem.

AVX2 Power Gating

In Skylake, AVX2 has been entirely power-gated. The motive for this change is derived from the fact that applications either make heavy use of AVX2 instructions or don't use it at all. Most programs seldomly use AVX2 for only a small number of instructions. This gave Intel the ability to completely power gate it when the core execute code that does not make use of those instructions. Skylake requires a warm-up time before instructions can execute at full rate (in the order of a couple of 10,000s of cycles depending on frequency). Executing a dummy AVX2 instruction some time prior to heavy AVX2 workloads to prepare the CPU can avoid this.

Clock domains

Skylake is divided into a number of clock domains, each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock (BCLK).

• BCLK - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual FSB speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz.
• Core Clock - The frequency at which the core and the L1/L2 caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).
• Ring Clock - The frequency at which the ring interconnect and LLC operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.
• IGP Clock - The frequency at which the integrated graphics (Gen9 GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.
• eDRAM Clock - The frequency at which the embedded DRAM operates at (only available for certain models). Data is read/written from/to the LLC at a rate of 32B/cycle operating at this frequency as well.
• MemClk - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transfered at a rate of 8B/cycle operating at MemClk frequency.

Overclocking

See also: Intel's XMP

Skylake has improved overclocking capabilities greatly. Overclocking is generally done on unlocked parts such as the Core i7-6700K, Core i5-6600K, and the mobile Core i7-6820HK processor. Unlocked processors should be paired with a chipset such as the Z170 which offers the most overclocking capabilities such as unlocked BCLK, unlocked core ratio, unlocked memory ratio, unlocked GPU ratio, and voltage controls.

Skylake increased both the overclocking range and ratio granularity, allowing for much more finer overclocking.

Note that core ratio has been increased to a [theoretical] x83 multiplier and the coarse-grain ratio was dropped from Skylake allowing a BCLK ratio to have granularity of 1 MHz increments with BCLK frequency of over 200 readily achievable. The FIVER was removed and the voltage control was given back to the motherboard manufacturers; i.e., voltage supplies can be entirely motherboard-controlled. Skylake also bumped the DDR ratio up to 4133 MT/s.

In the diagram on the left (xC) refers to the Core Frequency and is represented as a multiple of BCLK (Core Frequency = BCLK × Core Freq Multiplier up to x83). Likewise (xM) refers to the memory ratio (up to 4133 MT/s) and (xG) refers to the Graphics Frequency (pGfx; up to x60).

The BCLK in Skylake has undergone dramatic architectural changes. Considerable effort was dedicated to separating the DMI and PEG (PCIe & Graphics), allowing DMI/PEG to run at their nominal ~100 MHz clock in their own isolated clock domain. This allows BCLK to run at very high speeds (200 MHz+ with upward of 400 MHz+ in LN2). Additionally, while the BCLK is typically supplied by the chipset internal clock generator, it's also possible to supply the clock externally; i.e., motherboard ODMs can potentially take advantage of this and offer their own discrete BCLK control.

Overclocking may involve changing the BCLK frequency. Because a large number of components operate their own clock domains as a multiple of the BCLK, an increase of 10% to the BCLK frequency will result in an increase of 10% to all other components. On Skylake, the PCIe & DMI sit on their own dedicated reference clock.

The primary voltage rails on Skylake are the V_CORE = V_RING which can operate up to 1.52 V (SVID) + V_boost. V_DDQ is the typical 1.2 V nominal voltage for DDR4. V_GT refers to the graphics processor which can also operate up to 1.52 V (SVID) + V_boost. Lastly the V_SA refers to the system agent which has its own voltage control as well. Note that the ring voltage now runs at core voltage; Intel found no harm in overclocking and coupling them together. Additional rails are provided to the manufacturers which they can also expose for overclocking.

Voltage Control Modes

As with all of Intel's latest microarchitectures, Skylake incorporates a Power Control Unit (PCU) which is a dedicated microcontroller on-die in the System Agent. The PCU runs dedicated embedded firmware and makes dynamic power management decisions based on various global inputs such as temperature, current, power, and workload types.

The system can operate in a number of Voltage Control Modes. The mode chosen dictates how the PCU determines what voltage to use:

New Integration

Image Processing Unit (IPU)

Skylake integrates a new Image Processing Unit (IPU) on-die. The IPU is an entire imaging subsystem turnkey solution (i.e., ISP + hardware manipulation functionality), requiring only the external sensor camera. This feature is only available on the dual-core mobile models. The motivations behind this integration is primarily form factor the integrated IPU allows for higher user-end experience, and further power optimization.

The IPU hardware supports:

• 13 MP zero shutter lag 1080p60/2160p30 video capture and imaging and a large array of standardized image processing capabilities.
• Face detection and recognition (smile/blink/group setting)
• Full resolution still capture during video captures
• Multi-stream video captures (up to 2 concurrent streams)
• Panorama
• Burst Captures
• HDR ultra low-light captures

Die

Client Die

Skylake desktop and mobile come and 2 and 4 cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the GPU. The major components of the die is:

• System Agent
• CPU Core
• Ring bus interconnect
• Memory Controller

System Agent

The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), the I/O bus and various other shared functionality. Note that the mainstream desktop (i.e., quad-core die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be).

Dual-Core Die

Quad-Core Die

Core

Skylake Client models come in either 2x core or 4x core setup.

• ~3.95 mm x ~2.21 mm
• ~8.73 mm²

Core Group

Client models come in groups of 2 or 4 cores. (die sizes includes the dark silicon space where the L3 ends).

• 2-cores group:
• ~8.91 mm x ~2.845 mm
• ~25.347 mm²

• 4-core group
• ~8.844 mm x 5.694 mm
• ~50.354 mm²

Integrated Graphics

The integrated graphics takes up the largest portion of the die. The normal dual-core and quad-core dies come with 24 EU Gen9.5 GPU (with 12 units disabled on the low end models).

Dual-core

Die shot of the dual-core GT2 Skylake processors. Those are found in mobile models, and entry-level/budget processors:

• 14 nm process
• 11 metal layers
• ~1,750,000,000 transistors
• ~9.57 mm x ~10.3 mm
• ~98.57 mm² die size
• 2 CPU cores + 24 GPU EUs

Quad-core

Die shot of the quad-core GT2 Skyllake processors. Those are found in almost all mainstream desktop processors.

• 14 nm process
• 11 metal layers
• ~122 mm² die size
• 4 CPU cores + 24 GPU EUs

Server Die

Skylake Server class models and high-end desktop (HEDT) consist of 3 different dies: Low Core Count (LCC), Medium Core Count (MCC), and High Core Count (HCC).

Low Core Count (LCC)

This section is empty; you can help add the missing info by editing this page.

• 14 nm process
•  ? metal layers
• ~22.26 mm x ~14.62 mm
• ~325.44 mm² die size
• 10 cores

Medium Core Count (MCC)

Die shot of the octadeca core HEDT Skylake X processors.

• 14 nm process
•  ? metal layers
•  ? mm² die size
• 18 cores

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

High Core Count (HCC)

• 14 nm process
•  ? metal layers
•  ? mm² die size
• 28 cores

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Added instructions

SGX - Software Guard Extensions

MPX - Memory Protection Extensions

AVX-512 - Advanced Vector Extensions 512; These instructions can only be found Xeon models (codename Skylake SP) and HEDT processors (codename Skylake X)

All Skylake Chips

References

• 2014 Intel Developer Forum in San Francisco, September 9, 2014
• Julius Mandelblat, Senior Principal Engineer, Lead Architect, 2015 IDF in San Francisco, Session SPCS001 ("Technology Insight: Intel’s Next Generation Microarchitecture Code Name Skylake"), August 18, 2015
• Efraim Rotem, Senior Principal Engineer, Lead Client Power Architect, 2015 IDF in San Francisco, Session ARCS001 ("Intel® Architecture, Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency"), August 18, 2015
• David Blythe, Intel Fellow and Chief Graphics Software Architect, 2015 IDF in San Francisco, Session SPCS003 ("Technology Insight: Next Generation Intel® Processor Graphics Architecture, Code Name Skylake"), August 18, 2015
• Dan Ragland, Overclocking System Architect, 2015 IDF, in San Francisco, Session RPCS001 ("Overclocking 6th Generation Intel® Core™ Processors!"), August 18, 2015
• Jack Doweck, Intel, Hot Chips 28, 2016
• Fayneh, Eyal, et al. "4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.

Documents

• 6th Gen Intel® Core™ Mobile Processor Family: Platform Brief
• 6th Gen Intel® Core™ processor family and Intel® Xeon® processors Factsheet
• 6th Gen Intel® Core™ Processors: Y-series, U-series, and H-series Product Brief
• 6th Gen Intel® Core™ vPro™ Processor Family Product Brief
• 6th Generation Intel® Core™ Desktop Processors i7-6700K and i5-6600K Product Brief
• New Intel Core X-Series Processor Family

• Overclocking 6th Generation Intel® Core™ Processors
• Technology Insight Intel’s Next Generation Microarchitecture Code Name Skylake
• Intel Architecture, Code Name Skylake Deep Dive- A New Architecture to Manage Power Performance and Energy Efficiency

See also

• AMD Zen

External Links

• TOP 10 Z170 MOTHERBOARDs – Round-up, Multitechnopark (2016).