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Difference between revisions of "x86/extensions"
< x86

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| [[2013]] || {{x86|FMA3}} || {{intel|Haswell|l=arch}} || 3-operands fused multiply-add
 
| [[2013]] || {{x86|FMA3}} || {{intel|Haswell|l=arch}} || 3-operands fused multiply-add
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| [[2013]] || {{x86|TSX}} || {{intel|Haswell|l=arch}} || Transactional Synchronization Extensions; adds transactional memory support
 
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| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions
 
| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions
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| [[2015]] || {{x86|AVX-512}} || {{intel|Airmont|l=arch}} || 512 bit register operations
 
| [[2015]] || {{x86|AVX-512}} || {{intel|Airmont|l=arch}} || 512 bit register operations
 
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BMI / BMI1 + BMI2 / Bit Manipulation instructions
 

Revision as of 23:48, 24 November 2016

The x86 ISA has gone through numerous iterations that added new instructions to performs specific tasks. These collections of new instructions are grouped into extensions. Different microprocessor models have different levels of support for certain extensions.

Timeline

Extension First µarch Description
1978 Real 8086 Original Real mode
1982 Protected 80186 Protected mode
1985 SMM 80386 System Management Mode
1989 FPU 80486 Incorporates the x87 FPU into the same die
1996 MMX P5 First implementation for SIMD instructions
1998 3DNow! K6-2 SIMD extension for manipulating single-precision floating point
1999 SSE P5 Streaming SIMD Extensions, SIMD for single-precision floating point
1999 E3DNow! K7 Extended 3DNow! (New DSP instructions + some MMX instructions)
1999 Professional 3DNow! A name given by AMD for E3DNow! + SSE
1999 EMMX P6 Extended MMX; an extension to MMX
2001 SSE2 P6 Attempt to replace the original MMX instructions; use wider XMM registers have offer better performance
2004 SSE3 Core Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
2006 SSSE3 Core Supplemental Streaming SIMD Extensions 3; additional instructions for working with packed integers
2007 SSE4.1 Penryn Streaming SIMD Extensions 4.1; initial set of instructions for manipulating media data
2007 SSE4a K10 4 SIMD instructions, not related to 4.1/4.2
2007 ABM K10 Advanced Bit Manipulation; bit counting instructions
2008 SSE4.2 Nehalem Streaming SIMD Extensions 4.2; second set of instructions for manipulating media data
2007 SSE5 Proposed by AMD in 2007 but was never implemented
2008 SSE4 Streaming SIMD Extensions 4; SSE4.1
2009 XOP Bulldozer eXtended Operations; various vector operations
2010 CLMUL Westmere
2011 AVX Sandy Bridge Advanced Vector Extensions; introduces 256-bits integer operations
2012 F16C Ivy Bridge Extension for performing half-precision <-> single-precision conversions
2011 FMA4 Bulldozer 4-operands fused multiply-add
2011 AES Westmere Instructions for optimizing AES operations
2012 TBM Piledriver Trailing Bit Manipulation; bit manipulation instructions designed to be compiler intrinsics
2013 BMI1 Jaguar Bit Manipulation Instruction Set 1; introduces a number of bit manipulation instructions
2013 BMI2 Haswell Bit Manipulation Instruction Set 2; introduces additional bit manipulation instructions
2013 FMA3 Haswell 3-operands fused multiply-add
2013 TSX Haswell Transactional Synchronization Extensions; adds transactional memory support
2013 AVX2 Haswell Advanced Vector Extensions; additional instructions
2014 ADX Haswell Multi-Precision Add-Carry Instruction extension
2015 AVX-512 Airmont 512 bit register operations
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