Revision as of 18:38, 22 December 2025

Zen 5 is a microarchitecture Already released and sold being by AMD as a successor to Zen 4

History

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 ^[1]

Codenames

Product Codenames:

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server

processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").

Architectural Codenames:

Comparison

Process Technology

Zen 5 is to be produced on a 4 nm process, Zen 5c is to be produced on a 3 nm process.

Architecture

AMD Zen 5 released in July 2024. The seventh microarchitecture in the Zen microarchitecture series.

Codenamed Granite Ridge, Strix Point, and Turin, it is slated for TSMC 4 nm or 3 nm manufacturing.

• LITTLE design

- Improved 16% IPC and clock speed

- possibly more L3 cache per chiplet

Key changes from Zen 4

Core level (vs. Zen 4 microarchitectures)

• Instruction set

AVX-512 VP2INTERSECT support

AVX-VNNI support

• Front end

• Branch prediction improvements

- L1 BTB size increased significantly from 1.5K → 16K (10.7x)

- L2 BTB size increases from 7K → 8K

- Increased size of TAGE

- Introduction of 2-ahead predictor structure

- Return stack size increased from 32 → 52 entries (+62.5%)

• Improved instruction cache latency and bandwidth

- Instruction fetch bandwidth increased from 32B → 64B per cycle

- L2 instruction TLB size increased from 512 → 2048 entries (4x)

• Introducing a dual decode pipeline

- Decoder throughput scaled from 4 to 8 (2x4) per cycle (4 per thread, 4 in single thread)

- Op cache throughput expanded from 9 → 12 (2x6) per cycle (6 per thread, 6 for single thread)

- Unlike Intel E-Core, where a single thread can utilize multiple clusters, one cluster is used per SMT thread.

• Back end

• Dispatch width of integer operations expanded from 6 → 8

• The size of ROB (reorder buffer) has been expanded from 320 to 448 entries (+40%)

• Integer register file capacity expanded from 192 → 240 entries (+25%)

• Floating point register file capacity expanded from 192 to 384 entries (2x)

• Flag register file capacity expanded to 192 entries

• Increased size of integer scheduler

- Scheduler size expanded from 4x24 (=96) → 88+56 (=144) entries (+50%)

- Adoption of integrated scheduler configuration similar to Intel P-Core

• Increased size of floating point scheduler

- The size of the pre-scheduler queue has been expanded from 64 to 96 entries (+50%).

- Scheduler size expanded from 2x32 (=64) → 3x38 (=114) entries (+78%)

• Number of ALUs increased from 4 → 6 (+50%)

• Number of multiplication units increases from 1 → 3 (3x)

• Number of branch units increased from 2 → 3 (+50%)

• Number of AGU increased from 3 → 4 (+33%)

- Number of loads that can be processed per cycle increased from 3 → 4 (same as 2 for 128 bits or more)

- Number of 128/256 bit stores that can be processed per cycle increased from 1 → 2

Desktop and server products such as Granite Ridge can process AVX-512 SIMD in one cycle.

However, mobile products process 256 bits in two cycles like the previous Zen 4.

• Memory subsystem

• Load/Store Queue

- Increased size

• Prefetcher

- Added 2D stride prefetcher

- Improved stream & region prefetcher

• L1 data cache

- Capacity increased from 32 KB → 48 KB

- Associativity increases from 8-way → 12-way

- Bandwidth doubled

• L2 data cache

- Associativity increases from 8-way → 16-way

- Bandwidth increases from 32B → 64B per cycle

• L3 data cache

- Slight improvement in latency

- Maximum number of in-flight misses increased to 320

• Physical design

Improved power gating technology

• The overall expansion of the architecture has improved performance per clock

by an average of 16% compared to the previous generation.

Members

EPYC 9005 Series

"Turin/Turin Dense" (Server)

The fifth generation of EPYC processors was launched on October 10, 2024, at AMD's Advancing AI event, with general availability beginning in November 2024. Based on the Zen 5 microarchitecture, the 9005 series, codenamed "Turin", is manufactured by TSMC using a 4 nm process for standard Zen 5 cores and a 3 nm process for Zen 5c cores.

It utilizes the Socket SP5 socket, maintaining compatibility with the previous generation. The series offers core counts ranging from 8 cores to 192 cores, with support for up to 12 channels of DDR5-6000 memory (up to 6 TiB per socket) and 128 PCIe 5.0 lanes, enhancing performance and efficiency for high-performance computing, cloud, and AI workloads.

The series includes standard Zen 5 models, high-frequency "F" SKUs, single-socket "P" SKUs, and dense Zen 5c models, with TDPs ranging from 155 W to 500 W.

Ryzen 9000 Series

"Granite Ridge" (Desktop)

Model Name  	Cores/Threads Base/Boost Clock Cache (L3/L2)	Graphics (int.)	Memory Support	TDP

Ryzen 9 9950X3D2	16/32	4.3/5.6 GHz	192/16 MB	2x RDNA 2 CUs	DDR5-5600	200W
Ryzen 9 9950X3D		16/32	4.3/5.7 GHz	128/16 MB	2x RDNA 2 CUs	DDR5-5600	170W
Ryzen 9 9950X		16/32	4.3/5.7 GHz	 64/16 MB	2x RDNA 2 CUs	DDR5-5600	170W
Ryzen 9 PRO 9945	12/24	3.4/TBD GHz	 64/12 MB	2x RDNA 2 CUs	DDR5-5600	65W
Ryzen 9 9900X3D		12/24	4.4/5.5 GHz	128/12 MB	2x RDNA 2 CUs	DDR5-5600	120W
Ryzen 9 9900X		12/24	4.4/5.6 GHz	 64/12 MB	2x RDNA 2 CUs	DDR5-5600	120W
Ryzen 7 9850X3D		 8/16	4.7/5.6 GHz	 96/8 MB	2x RDNA 2 CUs	DDR5-5600	120W
Ryzen 7 9800X3D		 8/16	4.7/5.2 GHz	 96/8 MB	2x RDNA 2 CUs	DDR5-5600	120W
Ryzen 7 PRO 9745	 8/16	3.8/TBD GHz	 32/8 MB	2x RDNA 2 CUs	DDR5-5600	65W
Ryzen 7 9700X		 8/16	3.8/5.5 GHz	 32/8 MB	2x RDNA 2 CUs	DDR5-5600	65W/105W
Ryzen 7 9700F		 8/16	3.8/5.5 GHz	 32/8 MB	N/A		DDR5-5600	65W
Ryzen 5 PRO 9645	 6/12	3.9/TBD GHz	 32/6 MB	2x RDNA 2 CUs	DDR5-5600	65W
Ryzen 5 9600X3D		 6/12	3.9/TBD GHz	 96/6 MB	2x RDNA 2 CUs	DDR5-5600	65W
Ryzen 5 9600X		 6/12	3.9/5.4 GHz	 32/6 MB	2x RDNA 2 CUs	DDR5-5600	65W/105W
Ryzen 5 9600		 6/12	3.8/5.2 GHz	 32/6 MB	2x RDNA 2 CUs	DDR5-5600	65W

Ryzen AI 400 Series

"Gorgon Point" (APU)

Model Name  	Cores/Threads	Boost Clock	Cache	NPU	GPU	   Lanes  	TDP

Ryzen AI 9 HX 470	12/24	5.25 GHz+	36 MB	16 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 9 465		10/20	5.00 GHz	34 MB	12 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 7 460		 8/16	5.20 GHz+	24 MB	 8 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 7 450		 8/16	5.15 GHz+	24 MB	 8 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 7 445		 6/12	TBD		TBD	 4 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 5 440		 6/12	4.80 GHz	22 MB	 4 CU RDNA 3.5	16 PCIe Gen4	15-45W
Ryzen AI 5 435		 6/12	4.70 GHz	14 MB	 4 CU RDNA 3.5	14 PCIe Gen4	15-45W
Ryzen AI 5 430		 4/8	TBD		12 MB	 4 CU RDNA 3.5	14 PCIe Gen4	15-45W
Ryzen AI 3 420		 4/8	4.60 GHz	12 MB	 2 CU RDNA 3.5	14 PCIe Gen4	15-45W

EPYC Embedded 2005 Series

EPYC Embedded (Zen 5)

Model Name  	Cores/Threads	Base/Max Freq.	L3 Cache	TDP

EPYC Embedded 2875	16/32	3.0/4.5 GHz	64 MB		75 W
EPYC Embedded 2655	12/24	2.7/4.5 GHz	64 MB		55 W
EPYC Embedded 2435	 8/16	2.8/4.5 GHz	32 MB		45 W

Designers

• David Suggs, chief architect

Bibliography

See also

AMD • Zen • Ryzen • EPYC

Zen Naples Snowy Owl Whitehaven Summit Ridge Raven Ridge  Great Horned Owl Banded Kestrel • Power • Performance

Zen+ Colfax Pinnacle Ridge  Picasso Dali (Athlon) Pollock River Hawk • Power • Performance

Zen 2 Rome Castle Peak   Matisse Renoir Lucienne Mendocino Grey Hawk • Power • Performance

Zen 3 Milan Chagall Vermeer   Cezanne Barcelo • Power • Performance Zen 3+ Milan-X Badami Trento Rembrandt Rembrandt-R

Zen 4 Genoa Storm Peak Raphael Dragon Range   Hawk Point Phoenix • Power • Performance Zen 4c Siena Bergamo Phoenix 2

.

• Intel • Meteor Lake