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Difference between revisions of "amd/microarchitectures/zen 5"
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{{amd title|Zen 5|arch}}
 
{{amd title|Zen 5|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
| atype           = CPU
+
|atype=CPU
−
| name             = Zen 5
+
|name=Zen 5
−
| designer         = AMD
+
|designer=AMD
−
| manufacturer     = GlobalFoundries
+
|manufacturer=TSMC
−
| manufacturer 2   =  
+
|process=N4X
−
| introduction    =  
+
|cores=256
−
| phase-out        =  
+
|cores 2=224
−
| process          = 5 nm
+
|cores 3=192
−
 
+
|cores 4=144
−
| succession      = Yes
+
|cores 5=128
−
| predecessor     = Zen 3
+
|cores 6=96
−
| predecessor link = amd/microarchitectures/zen 3
+
|cores 7=72
−
| successor       =  
+
|cores 8=64
−
| successor link  =  
+
|cores 9=56
 +
|cores 10=48
 +
|cores 11=32
 +
|cores 12=28
 +
|cores 13=36
 +
|cores 14=24
 +
|cores 18=18
 +
|cores 16=16
 +
|cores 8=8
 +
|cores 6=6
 +
|processing elements=512
 +
|processing elements 2=448
 +
|processing elements 3=384
 +
|processing elements 4=288
 +
|processing elements 5=256
 +
|processing elements 6=192
 +
|processing elements 7=144
 +
|processing elements 8=128
 +
|processing elements 9=112
 +
|processing elements 10=96
 +
|processing elements 11=64
 +
|processing elements 12=56
 +
|processing elements 13=60
 +
|processing elements 14=40
 +
|processing elements 15=30
 +
|processing elements 16=20
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|isa=x86-64
 +
|isa 2=AVX512, AMX (Advanced Matrix Extensions)
 +
|feature=SHA
 +
|feature 2=XFR 3 or 4 ( Extended frequency range)
 +
|core name=Turin (EPYC server multiprocessor)
 +
|core name 2=Da Vinci (Threadripper Workstation)
 +
|core name 3=Granite Ridge (Gaming Desktop CPU)
 +
|core name 4=Strix Point (Gaming APU with RDNA3 or RDNA4)
 +
|predecessor=Zen 4
 +
|predecessor link=amd/microarchitectures/zen 4
 +
|successor=Zen 6 or maybe a completely new microarchitecture
 +
|succession=Yes
 
}}
 
}}
−
'''Zen 5''' is a planned [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen 3}}.
+
'''Zen 5''' is a [[microarchitecture]]Already released and sold being by [[AMD]] as a successor to {{\\|Zen 4}}.
  
 
== History ==
 
== History ==
−
Zen 5 was first mentioned by Mark Clark during a interview in April of 2018. Zen 5 will be the 4rd iteration of the {{\\|Zen}} microarchitecture. The number four has been skipped because it brings bad luck in Chinese culture. It will probably be produced on a [[5nm process]].  
+
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen™ Processors: One Year Later]</ref>.
  
 
== Codenames ==
 
== Codenames ==
−
{{empty section}}
+
'''Product Codenames:'''
 +
{| class="wikitable"
 +
|-
 +
! Core !! C/T !! Target
 +
|-
 +
| {{amd|Turin|l=core}} || Up to ?/? || High-end server [[multiprocessors]]
 +
|-
 +
| {{amd|Da Vinci|l=core}} || Up to ?/? || Workstation & enthusiasts market processors
 +
|-
 +
| {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors
 +
|-
 +
| {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU
 +
|}
 +
 
 +
'''Architectural Codenames:'''
 +
{| class="wikitable"
 +
|-
 +
! Arch !! Codename
 +
|-
 +
| Core || Nirvana
 +
|-
 +
| CCD || Eldora
 +
|}
 +
 
 +
== Process Technology ==
 +
Zen 5 is to be produced on a 4nm process,Zen 5c is to be produced on a 3nm process.
  
 
== Architecture ==
 
== Architecture ==
−
Nothing is currently known about the architectural improvements that are being done to Zen 5.
 
  
−
=== Key changes from {{\\|Zen 3}} ===
+
LITTLE design
 +
-Improved 16% IPC and clock speed
 +
- possibly more L3 cache per chiplet
 +
 
 +
=== Key changes from {{\\|Zen 4}} ===
 
{{empty section}}
 
{{empty section}}
 +
 +
== Designers ==
 +
* David Suggs, chief architect
 +
 +
== Bibliography ==
 +
{{reflist}}
  
 
== See Also ==
 
== See Also ==
 
* AMD {{\\|Zen}}
 
* AMD {{\\|Zen}}
−
* Intel {{intel|Alder lake|l=arch}}
+
* Intel {{intel|Meteor Lake|l=arch}}

Latest revision as of 11:54, 29 October 2024

Edit Values
Zen 5 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
ProcessN4X
Core Configs256, 224, 192, 144, 128, 6, 72, 8, 56, 48, 32, 28, 36, 24
PE Configs512, 448, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64, AVX512, AMX (Advanced Matrix Extensions)
Cores
Core NamesTurin (EPYC server multiprocessor),
Da Vinci (Threadripper Workstation),
Granite Ridge (Gaming Desktop CPU),
Strix Point (Gaming APU with RDNA3 or RDNA4)
Succession

Zen 5 is a microarchitectureAlready released and sold being by AMD as a successor to Zen 4.

History[edit]

Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018[1].

Codenames[edit]

Product Codenames:

Core C/T Target
Turin Up to ?/? High-end server multiprocessors
Da Vinci Up to ?/? Workstation & enthusiasts market processors
Granite Ridge Up to ?/? Mainstream to high-end desktops & enthusiasts market processors
Strix Point Up to ?/? Mainstream desktop & mobile processors with GPU

Architectural Codenames:

Arch Codename
Core Nirvana
CCD Eldora

Process Technology[edit]

Zen 5 is to be produced on a 4nm process,Zen 5c is to be produced on a 3nm process.

Architecture[edit]

LITTLE design -Improved 16% IPC and clock speed - possibly more L3 cache per chiplet

Key changes from Zen 4[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Designers[edit]

  • David Suggs, chief architect

Bibliography[edit]

  1. ↑ Ryzen™ Processors: One Year Later

See Also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_5&oldid=102585"
Facts about "Zen 5 - Microarchitectures - AMD"
RDF feed
codenameZen 5 +
core count256 +, 224 +, 192 +, 144 +, 128 +, 6 +, 72 +, 8 +, 56 +, 48 +, 32 +, 28 +, 36 + and 24 +
designerAMD +
full page nameamd/microarchitectures/zen 5 +
instance ofmicroarchitecture +
instruction set architecturex86-64 + and AVX512, AMX (Advanced Matrix Extensions) +
manufacturerTSMC +
microarchitecture typeCPU +
nameZen 5 +
processing element count512 +, 448 +, 384 +, 288 +, 256 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 +