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Difference between revisions of "intel/cpuid"
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(Update the stepping for Family 7 Model 85, according to arch/x86/include/asm/intel-family.h in the linux kernel sources)
(→‎Family 4)
 
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== CPUIDs==
 
== CPUIDs==
 
=== Family 19 ===
 
=== Family 19 ===
−
{| class="wikitable"
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
|-
 
! Microarchitecture !! Core !! Platform !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 
! Microarchitecture !! Core !! Platform !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 
|-
 
|-
−
| {{intel|Diamond Rapids|l=arch}} <br> ([[2025]])|| Panther Cove X || Mountain Stream || 0x4 || 0xF || 0x0 || 0x1 || [[Family 19 Model 1]]
+
! {{intel|Diamond Rapids|l=arch}} <br>([[2025]])  
 +
| {{intel|Panther Cove X|l=core}} (P) • 18A <br>DMR-AP/SP (LGA9324) || Mountain <br>Stream || 0x4 || 0xF || 0x0 || 0x1 || [[Family 19 Model 1]]  
 +
|-
 +
! {{intel|Nova Lake|l=arch}} <br>([[2026]])
 +
| {{intel|Coyote Cove|l=core}} (P) • 18A<br>{{intel|Arctic Wolf|l=core}} (E) • NVL-S/H || || 0x4 || 0xF || 0x0 || 0x0 || [[Family 19 Model 0]]
 +
|-
 
|}
 
|}
−
Key changes from {{intel|Granite Rapids|l=arch}}: '''Core''': Redwood Cove+ → Panther Cove X, '''Platform''': Eagle Stream → Mountain Stream
+
 
 +
Key changes from {{intel|Granite Rapids|l=arch}}:  
 +
:• '''Core''': Redwood Cove+ → Panther Cove X (P-core), '''Platform''': Eagle Stream → Mountain Stream
 +
<!--https://avatars.dzeninfra.ru/get-zen_doc/271828/pub_676cd4817ee72809045dd2bf_676cd4857ee72809045dd703/scale_1200-->
  
 
=== Family 15 ===
 
=== Family 15 ===
−
{| class="wikitable"
+
:;• [[Intel]] • [[Core]] • {{intel|Xeon}}
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
|-
 +
! Microarchitecture !! Core !! Fab node !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model
 +
|-
 +
! {{intel|Modified Pentium M|l=arch}} <br>([[2006]])
 +
| {{intel|Cedar Mill|l=core}} (2C) <br>({{intel|Xeon}} {{intel|Dempsey|l=core}}) || [[65 nm]] || 0 || 0xF || 0x0 || 0x6 || [[Family 15 Model 6]]
 
|-
 
|-
−
| rowspan="5" | {{intel|Netburst|l=arch}} (P68) <br>([[2000]]) || || 0 || 0xF || 0x0 || 0x6 || [[Family 15 Model 6]]
+
! rowspan="4" | {{intel|Netburst|l=arch}} (P68) <br>([[2000]])  
 +
| {{intel|Prescott|l=core}} (2M) || [[90 nm]] || 0 || 0xF || 0x0 || 0x4 || [[Family 15 Model 4]]
 
|-
 
|-
−
| {{intel|Prescott|l=core}} (90nm) || 0 || 0xF || 0x0 || 0x4 || [[Family 15 Model 4]]
+
| {{intel|Prescott|l=core}} || [[90 nm]] || 0 || 0xF || 0x0 || 0x3 || [[Family 15 Model 3]]
 
|-
 
|-
−
| {{intel|Prescott|l=core}} (90nm) || 0 || 0xF || 0x0 || 0x3 || [[Family 15 Model 3]]
+
| {{intel|Northwood|l=core}} || [[130 nm]] || 0 || 0xF || 0x0 || 0x2 || [[Family 15 Model 2]]
 
|-
 
|-
−
| {{intel|Northwood|l=core}} (130nm) || 0 || 0xF || 0x0 || 0x2 || [[Family 15 Model 2]]
+
| {{intel|Willamette|l=core}}<br>({{intel|Xeon}} {{intel|Foster|l=core}}) || [[180 nm]] || 0 || 0xF || 0x0 || 0x1 || [[Family 15 Model 1]]
 
|-
 
|-
−
| {{intel|Willamette|l=core}} (180nm) || 0 || 0xF || 0x0 || 0x1 || [[Family 15 Model 1]]
 
 
|}
 
|}
 +
<!--
 +
/* Family 15 - NetBurst */
 +
#define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */
 +
#define INTEL_P4_PRESCOTT IFM(15, 0x03)
 +
#define INTEL_P4_PRESCOTT_2M IFM(15, 0x04)
 +
#define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey
 +
-->
  
 
=== Family 11 ===
 
=== Family 11 ===
−
{| class="wikitable"
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
|-
 +
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 
|-
 
|-
−
| {{intel|Knights Corner|l=arch}} ([[2011]]) || [[62 cores]] ([[22 nm]]) || 0 || 0xB || 0x0 || 0x1 || [[Family 11 Model 1]]
+
| '''{{intel|Knights Corner|l=arch}}''' ([[2011]]) || [[62 cores]] ([[22 nm]]) || 0 || 0xB || 0x0 || 0x1 || [[Family 11 Model 1]]
 
|-
 
|-
−
| {{intel|Knights Ferry|l=arch}} ([[2010]]) || [[32 cores]] ([[45 nm]]) || 0 || 0xB || 0x0 || 0x0 || [[Family 11 Model 0]]
+
| '''{{intel|Knights Ferry|l=arch}}''' ([[2010]]) || [[32 cores]] ([[45 nm]]) || 0 || 0xB || 0x0 || 0x0 || [[Family 11 Model 0]]
 
|-
 
|-
 
|}
 
|}
Line 38: Line 60:
 
=== Family 6 ===
 
=== Family 6 ===
 
==== {{intel|MIC Architecture}} ====
 
==== {{intel|MIC Architecture}} ====
−
{| class="wikitable"
+
:;• [[Xeon Phi]] •
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
|-
 +
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 +
|-
 +
| '''{{intel|Knights Mill|l=arch}}'''<br><s>{{intel|Knights Hill|l=arch}}</s>, <br><s>{{intel|Knights Peak|l=arch}}</s> || [[Xeon Phi]]<br>64C/256T <br>[[14 nm]] || 0 || 0x6 || 0x8 || 0x5 || [[Family 6 Model 133]]
 
|-
 
|-
−
| {{intel|Knights Mill|l=arch}} || || 0 || 0x6 || 0x8 || 0x5 || [[Family 6 Model 133]]
+
| '''{{intel|Knights Landing|l=arch}}''' || [[Xeon Phi]]<br>72C/288T <br>[[14 nm]] || 0 || 0x6 || 0x5 || 0x7 || [[Family 6 Model 87]]
 
|-
 
|-
−
| {{intel|Knights Landing|l=arch}} || || 0 || 0x6 || 0x5 || 0x7 || [[Family 6 Model 87]]
 
 
|}
 
|}
 +
<!--
 +
/* Xeon Phi */
 +
#define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */
 +
#define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */
 +
-->
  
 
==== [[Small Cores]] ====
 
==== [[Small Cores]] ====
−
Intel's client small cores refers to Intel low-power SoCs that ship in low power  
+
[[Intel]]'s client [[small core]]s refers to [[Intel]] low-power SoCs that ship in low power  
 
:laptops, tablets, embedded devices, and low-power servers.
 
:laptops, tablets, embedded devices, and low-power servers.
 +
<!-- * "Small Cores" Processors (Atom/E-Core) */
 +
#define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */
 +
#define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */
 +
#define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */
 +
#define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alder Lake N */
 +
#define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */
 +
#define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */
 +
#define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest *
 +
 +
Intel Atom
 +
10 nm • Tremont 2020 • Lakefield (hybrid) • Elkhart Lake • Jasper Lake • Jacobsville • Parker Ridge • Snow Ridge
 +
Intel 7 nm • Gracemont 2021 • Alder Lake (hybrid) • Alder Lake S (N/P/M) • Raptor Lake (S) (hybrid) • Twin Lake
 +
Intel 4 nm • Crestmont 2023 • Meteor Lake (hybrid) • Grand Ridge
 +
TSMC N6 6 nm • Intel 3 nm 2024 Sierra Forest
 +
TSMC N3B • Skymont 2024 Lunar Lake (hybrid) • Arrow Lake (hybrid)
 +
Intel 18A • Darkmont 2025 Clearwater Forest
 +
 +
Wildcat Lake (2025) Cougar Cove (P) • Darkmont (LPE)
 +
• WCL, 2P+4LPE 0 0x6 0xC 0xD ? ?
 +
Panther Lake (2025) Cougar Cove (P)  • Darkmont (E)
 +
• PTL-U/H/P 0 0x6 0xC 0xC -->
  
−
{| class="wikitable"
+
:;• "[[Small Cores]]" Processors ([[Intel Atom|Atom]]/E-[[Core]]) •
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
|-
 +
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 +
|-
 +
! {{intel|Darkmont|l=arch}}<br>([[2025]])
 +
| {{intel|Clearwater Forest|l=arch}}<br>CWF-AP/CWF-SP<hr>{{intel|Wildcat Lake|l=arch}} WCL<hr>{{intel|Panther Lake|l=arch}} U/H/P || 0 || 0x6 || .<br>0xD<hr>0x?<hr>0xC || .<br>0xD<hr>0x?<hr>0xC || ''Darkmont_X''<br>IFM (6, 0xDD)<hr>.<hr>.
 +
|-
 +
! {{intel|Skymont}}<br>([[2024]])
 +
| {{intel|Arrow Lake|l=arch}} S/U <hr>{{intel|Lunar Lake|l=arch}} MX/V || 0 || 0x6 || 0xB<hr>0xB || 0x5<hr>0xC || 0xB 0x5, 0xC 0x5/0x6<hr>0xB 0xC/0xD
 +
|-
 +
! {{intel|Crestmont|l=arch}}<br>([[2023]])
 +
| {{intel|Sierra Forest|l=arch}} SP <hr>{{intel|Meteor Lake|l=arch}} S/N <hr>{{intel|Grand Ridge|l=arch}} || 0 || 0x6 || 0xA<hr>0xA<hr>0xB || 0xF<hr>0xA<hr>0x6 || IFM (6, 0xAF) <hr>0xA, 0xB, 0xC <hr>IFM (6, 0xB6)
 
|-
 
|-
−
| rowspan="3" | {{intel|Tremont|l=arch}} || {{intel|Jasper Lake|l=core}} || 0 || 0x6 || 0x9 || 0xC || [[Family 6 Model 156]]
+
! {{intel|Gracemont|l=arch}}<br>([[2021]])
 +
| {{intel|Alder Lake|l=arch}} N <hr>{{intel|Raptor Lake|l=arch}} S/N<hr>{{intel|Twin Lake|l=arch}} S || 0 || 0x6 || 0xB<hr>0xB<hr>0x? || 0xE<hr>0x7<hr>0x? || IFM (6, 0xBE) <!--(S/N/P/M), S: 0x9 0x7, P: 0x9 0xA)--> <hr>0xB 0x7/0xB 0xE <hr>?
 +
|- <!-- + Jacobsville √ • Parker Ridge ? • Snow Ridge ? -->
 +
! rowspan="4" | {{intel|Tremont|l=arch}}<br>([[2020]])
 +
| {{intel|Jasper Lake|l=core}} (L) || 0 || 0x6 || 0x9 || 0xC || [[Family 6 Model 156]]
 
|-
 
|-
 
| {{intel|Elkhart Lake|l=core}} || 0 || 0x6 || 0x9 || 0x6 || [[Family 6 Model 150]]
 
| {{intel|Elkhart Lake|l=core}} || 0 || 0x6 || 0x9 || 0x6 || [[Family 6 Model 150]]
 +
|-
 +
| {{intel|Jacobsville|l=core}} (D) || 0 || 0x6 || 0x8 || 0x6 || IFM (6, 0x86)
 
|-
 
|-
 
| {{intel|Lakefield|l=arch}} || 0 || 0x6 || 0x8 || 0xA || [[Family 6 Model 138]]
 
| {{intel|Lakefield|l=arch}} || 0 || 0x6 || 0x8 || 0xA || [[Family 6 Model 138]]
 
|-
 
|-
−
| {{intel|Goldmont Plus|l=arch}} || {{intel|Gemini Lake|l=core}} || 0 || 0x6 || 0x7 || 0xA || [[Family 6 Model 122]]
+
! {{intel|Goldmont Plus|l=arch}}  
 +
| {{intel|Gemini Lake|l=core}} || 0 || 0x6 || 0x7 || 0xA || [[Family 6 Model 122]]
 +
|-
 +
! rowspan="2" | {{intel|Goldmont|l=arch}}
 +
| {{intel|Denverton|l=core}} (D) || 0 || 0x6 || 0x5 || 0xF || [[Family 6 Model 95]]
 +
|-
 +
| {{intel|Apollo Lake|l=core}}, <br><s>{{intel|Broxton|l=core}}, <br>{{intel|Willow Trail|l=core}}</s> || 0 || 0x6 || 0x5 || 0xC || [[Family 6 Model 92]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Goldmont|l=arch}} || {{intel|Denverton|l=core}} || 0 || 0x6 || 0x5 || 0xF || [[Family 6 Model 95]]
+
! rowspan="2" | {{intel|Airmont|l=arch}}  
 +
| {{intel|Cherry Trail|l=core}}, <br>{{intel|Braswell|l=core}} || 0 || 0x6 || 0x4 || 0xC || [[Family 6 Model 76]]
 
|-
 
|-
−
| {{intel|Apollo Lake|l=core}}, <br><s>{{intel|Broxton|l=core}}</s> || 0 || 0x6 || 0x5 || 0xC || [[Family 6 Model 92]]
+
| Lightning <br>Mountain <small>(NP)</small> || 0 || 0x6 || 0x7 || 0x5 || IFM (6, 0x75)
 
|-
 
|-
−
| {{intel|Airmont|l=arch}} || {{intel|Cherry Trail|l=core}}, <br>{{intel|Braswell|l=core}} || 0 || 0x6 || 0x4 || 0xC || [[Family 6 Model 76]]
+
! rowspan="5" | {{intel|Silvermont|l=arch}}  
 +
| {{intel|SoFIA|l=core}} || 0 || 0x6 || 0x5 || 0xD || [[Family 6 Model 93]]
 
|-
 
|-
−
| rowspan="5" | {{intel|Silvermont|l=arch}} || {{intel|SoFIA|l=core}} || 0 || 0x6 || 0x5 || 0xD || [[Family 6 Model 93]]
+
| {{intel|Anniedale|l=core}} <small>(MID2)</small> || 0 || 0x6 || 0x5 || 0xA || [[Family 6 Model 90]]
 
|-
 
|-
−
| {{intel|Anniedale|l=core}} || 0 || 0x6 || 0x5 || 0xA || [[Family 6 Model 90]]
+
| {{intel|Avoton|l=core}}, <br>{{intel|Rangeley|l=core}} <small>(D)</small> || 0 || 0x6 || 0x4 || 0xD || [[Family 6 Model 77]]
 
|-
 
|-
−
| {{intel|Avoton|l=core}}, <br>{{intel|Rangeley|l=core}} || 0 || 0x6 || 0x4 || 0xD || [[Family 6 Model 77]]
+
| {{intel|Merriefield|l=core}}, <br>{{intel|Tangier|l=core}} <small>(MID)</small> || 0 || 0x6 || 0x4 || 0xA || [[Family 6 Model 74]]
 
|-
 
|-
−
| {{intel|Tangier|l=core}} || 0 || 0x6 || 0x4 || 0xA || [[Family 6 Model 74]]
+
| {{intel|Bay Trail|l=core}}, <br>Valleyview || 0 || 0x6 || 0x3 || 0x7 || [[Family 6 Model 55]]  
 
|-
 
|-
−
| {{intel|Bay Trail|l=core}} || 0 || 0x6 || 0x3 || 0x7 || [[Family 6 Model 55]]
+
! rowspan="3" | {{intel|Saltwell|l=arch}}
 +
| {{intel|Cedarview|l=core}} || 0 || 0x6 || 0x3 || 0x6 || [[Family 6 Model 54]]
 
|-
 
|-
−
| rowspan="3" | {{intel|Saltwell|l=arch}} || {{intel|Cedarview|l=core}} || 0 || 0x6 || 0x3 || 0x6 || [[Family 6 Model 54]]
+
| {{intel|Cloverview|l=core}} <small>(TAB)</small> || 0 || 0x6 || 0x3 || 0x5 || [[Family 6 Model 53]]
 
|-
 
|-
−
| {{intel|Cloverview|l=core}} || 0 || 0x6 || 0x3 || 0x5 || [[Family 6 Model 53]]
+
| {{intel|Penwell|l=core}} <small>(MID)</small> || 0 || 0x6 || 0x2 || 0x7 || [[Family 6 Model 39]]
 
|-
 
|-
−
| {{intel|Penwell|l=core}} || 0 || 0x6 || 0x2 || 0x7 || [[Family 6 Model 39]]
+
! rowspan="2" | {{intel|Bonnell|l=arch}}
 +
| {{intel|Silverthorne|l=core}}, <br>{{intel|Lincroft|l=core}} <small>(MID)</small> || 0 || 0x6 || 0x2 || 0x6 || [[Family 6 Model 38]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Bonnell|l=arch}} || {{intel|Lincroft|l=core}} || 0 || 0x6 || 0x2 || 0x6 || [[Family 6 Model 38]]
+
| {{intel|Diamondville|l=core}}, <br>{{intel|Pineview|l=core}} || 0 || 0x6 || 0x1 || 0xC || [[Family 6 Model 28]]
 
|-
 
|-
−
| {{intel|Silverthorne|l=core}}, <br>{{intel|Diamondville|l=core}}, <br>{{intel|Pineview|l=core}} || 0 || 0x6 || 0x1 || 0xC || [[Family 6 Model 28]]
 
 
|}
 
|}
 +
<!--
 +
* "Small Core" Processors (Atom/E-Core) */
 +
 +
#define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */
 +
#define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */
 +
 +
#define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */
 +
#define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */
 +
#define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */
 +
 +
#define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */
 +
#define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */
 +
#define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */
 +
#define INTEL_ATOM_SILVERMONT_MID2 IFM(6, 0x5A) /* Anniedale */
 +
 +
#define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */
 +
#define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */
 +
 +
#define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */
 +
#define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */
 +
 +
/* Note: the micro-architecture is "Goldmont Plus" */
 +
#define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */
 +
 +
#define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */
 +
#define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */
 +
#define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */
 +
 +
#define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */
 +
 +
#define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */
 +
#define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */
 +
 +
#define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest *
 +
-->
  
 
==== [[Big Cores]] (Server) ====
 
==== [[Big Cores]] (Server) ====
Line 92: Line 204:
 
:in most enterprise desktops, workstations, and servers.
 
:in most enterprise desktops, workstations, and servers.
  
−
{| class="wikitable"
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
|-
−
|- <!-- Clearwater Forest: 0xdd; Snow Ridge -> Grand Ridge: 0xb6 -->
+
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
−
| {{intel|Clearwater Forest|l=arch}} ([[2025]]) || ? || 0 || 0x6 || 0xD || 0xD || [[Family 6 Model 221]]
+
|- <!-- Clearwater Forest: 0xdd (Atom) • 2026 ? Intel 18A; Snow Ridge -> Grand Ridge: 0xb6 • Xeon -->
−
|- <!-- Sierra Forest: 0xaf -->
+
| '''{{intel|Clearwater Forest|l=arch}}''' <br>([[2025]]) || CWF-AP (LGA7529)<br>Darkmont (E) • 18A <br>CWF-SP (LGA4710) || 0 || 0x6 || 0xD || 0xD || [[Family 6 Model 221]]
−
| {{intel|Sierra Forest|l=arch}} ([[2024]]) || Crestmont SP || 0 || 0x6 || 0xA || 0xF || [[Family 6 Model 175]]
+
|- <!-- Sierra Forest: 0xaf (Atom) -->
 +
| '''{{intel|Sierra Forest|l=arch}}''' <br>([[2024]]) || Crestmont (E) SP <br>SRF-SP || 0 || 0x6 || 0xA || 0xF || [[Family 6 Model 175]]
 
|- <!-- Granite Rapids: 0xad, Granite Rapids D: 0xae; Core: Golden Cove → Redwood Cove -->
 
|- <!-- Granite Rapids: 0xad, Granite Rapids D: 0xae; Core: Golden Cove → Redwood Cove -->
−
| rowspan="2" | {{intel|Granite Rapids|l=arch}} ([[2024]]) || Redwood Cove D || 0 || 0x6 || 0xA || 0xE || [[Family 6 Model 174]]
+
| rowspan="2" | '''{{intel|Granite Rapids|l=arch}}''' <br>([[2024]]) || Redwood Cove (D) || 0 || 0x6 || 0xA || 0xE || [[Family 6 Model 174]]
 
|-
 
|-
 
| Redwood Cove || 0 || 0x6 || 0xA || 0xD || [[Family 6 Model 173]]
 
| Redwood Cove || 0 || 0x6 || 0xA || 0xD || [[Family 6 Model 173]]
 
|-
 
|-
−
| {{intel|Emerald Rapids|l=arch}} ([[2023]]) || {{intel|Golden Cove|l=arch}} || 0 || 0x6 || 0xC || 0xF || [[Family 6 Model 207]]
+
| '''{{intel|Emerald Rapids|l=arch}}''' <br>([[2023]]) || {{intel|Golden Cove|l=arch}} || 0 || 0x6 || 0xC || 0xF || [[Family 6 Model 207]]
 
|-
 
|-
−
| {{intel|Sapphire Rapids|l=arch}} ([[2023]]) || {{intel|Golden Cove|l=arch}} SP || 0 || 0x6 || 0x8 || 0xF || [[Family 6 Model 143]]  
+
| '''{{intel|Sapphire Rapids|l=arch}}''' <br>([[2023]]) || {{intel|Golden Cove|l=arch}} SP || 0 || 0x6 || 0x8 || 0xF || [[Family 6 Model 143]]  
 
|-
 
|-
−
| rowspan="2" | {{intel|Ice Lake (Server)|l=arch}} || {{intel|Ice Lake DE|DE|l=core}} || 0 || 0x6 || 0x6 || 0xC || [[Family 6 Model 108]]
+
| rowspan="2" | '''{{intel|Ice Lake (Server)|l=arch}}''' || {{intel|Ice Lake DE|DE|l=core}} || 0 || 0x6 || 0x6 || 0xC || [[Family 6 Model 108]]
 
|-
 
|-
 
| {{intel|Ice Lake SP|SP|l=core}} || 0 || 0x6 || 0x6 || 0xA || [[Family 6 Model 106]]
 
| {{intel|Ice Lake SP|SP|l=core}} || 0 || 0x6 || 0x6 || 0xA || [[Family 6 Model 106]]
 
|-
 
|-
−
| {{intel|Cooper Lake|l=arch}} (stepping 11) || ? || rowspan="3" | 0 || rowspan="3" | 0x6 || rowspan="3" | 0x5 || rowspan="3" | 0x5 || rowspan="3" | [[Family 6 Model 85]]
+
| '''{{intel|Cooper Lake|l=arch}}''' (stepping 11) || ? || rowspan="3" | 0 || rowspan="3" | 0x6 || rowspan="3" | 0x5 || rowspan="3" | 0x5 || rowspan="3" | [[Family 6 Model 85]]
 
|-
 
|-
−
| {{intel|Cascade Lake|l=arch}} (stepping 5-7) || {{intel|Cascade Lake SP|SP|l=core}}, {{intel|Cascade Lake X|X|l=core}}, {{intel|Cascade Lake W|W|l=core}}  
+
| '''{{intel|Cascade Lake|l=arch}}''' (stepping 5-7) || {{intel|Cascade Lake SP|SP|l=core}}, {{intel|Cascade Lake X|X|l=core}}, {{intel|Cascade Lake W|W|l=core}}  
 
|-
 
|-
−
| {{intel|Skylake (Server)|l=arch}} || {{intel|Skylake SP|SP|l=core}}, {{intel|Skylake X|X|l=core}}, {{intel|Skylake DE|DE|l=core}}, {{intel|Skylake W|W|l=core}}
+
| '''{{intel|Skylake (Server)|l=arch}}''' || {{intel|Skylake SP|SP|l=core}}, {{intel|Skylake X|X|l=core}}, {{intel|Skylake DE|DE|l=core}}, {{intel|Skylake W|W|l=core}}
 
|-
 
|-
−
| rowspan="2" |  {{intel|Broadwell (Server)|l=arch}} || {{intel|Broadwell DE|DE|l=core}}, {{intel|Hewitt Lake|l=core}} || 0 || 0x6 || 0x5 || 0x6 || [[Family 6 Model 86]]
+
| rowspan="2" |  {{intel|Broadwell|Broadwell (Server)|l=arch}} || {{intel|Broadwell DE|DE|l=core}}, {{intel|Hewitt Lake|l=core}} || 0 || 0x6 || 0x5 || 0x6 || [[Family 6 Model 86]]
 
|-
 
|-
 
| {{intel|Broadwell E|E|l=core}}, {{intel|Broadwell EP|EP|l=core}}, {{intel|Broadwell EX|EX|l=core}} || 0 || 0x6 || 0x4 || 0xF || [[Family 6 Model 79]]
 
| {{intel|Broadwell E|E|l=core}}, {{intel|Broadwell EP|EP|l=core}}, {{intel|Broadwell EX|EX|l=core}} || 0 || 0x6 || 0x4 || 0xF || [[Family 6 Model 79]]
 
|-
 
|-
−
| {{intel|Haswell (Server)|l=arch}} || {{intel|Haswell E|E|l=core}}, {{intel|Haswell EP|EP|l=core}}, {{intel|Haswell EX|EX|l=core}} || 0 || 0x6 || 0x3 || 0xF || [[Family 6 Model 63]]
+
| {{intel|Haswell|Haswell (Server)|l=arch}} || {{intel|Haswell E|E|l=core}}, {{intel|Haswell EP|EP|l=core}}, {{intel|Haswell EX|EX|l=core}} || 0 || 0x6 || 0x3 || 0xF || [[Family 6 Model 63]]
 
|-
 
|-
−
| {{intel|Ivy Bridge (Server)|l=arch}} || {{intel|Ivy Bridge E|E|l=core}}, {{intel|Ivy Bridge EN|EN|l=core}}, {{intel|Ivy Bridge EP|EP|l=core}}, {{intel|Ivy Bridge EX|EX|l=core}} || 0 || 0x6 || 0x3 || 0xE || [[Family 6 Model 62]]
+
| {{intel|Ivy Bridge|Ivy Bridge (Server)|l=arch}} || {{intel|Ivy Bridge E|E|l=core}}, {{intel|Ivy Bridge EN|EN|l=core}}, {{intel|Ivy Bridge EP|EP|l=core}}, {{intel|Ivy Bridge EX|EX|l=core}} || 0 || 0x6 || 0x3 || 0xE || [[Family 6 Model 62]]
 
|-
 
|-
−
| {{intel|Sandy Bridge (Server)|l=arch}} || {{intel|Sandy Bridge E|E|l=core}}, {{intel|Sandy Bridge EN|EN|l=core}}, {{intel|Sandy Bridge EP|EP|l=core}} || 0 || 0x6 || 0x2 || 0xD || [[Family 6 Model 45]]
+
| {{intel|Sandy Bridge|Sandy Bridge (Server)|l=arch}} || {{intel|Sandy Bridge E|E|l=core}}, {{intel|Sandy Bridge EN|EN|l=core}}, {{intel|Sandy Bridge EP|EP|l=core}} || 0 || 0x6 || 0x2 || 0xD || [[Family 6 Model 45]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Westmere (Server)|l=arch}} || {{intel|Westmere EX|EX|l=core}} || 0 || 0x6 || 0x2 || 0xF || [[Family 6 Model 47]]
+
| rowspan="2" | {{intel|Westmere|Westmere (Server)|l=arch}} || {{intel|Westmere EX|EX|l=core}} || 0 || 0x6 || 0x2 || 0xF || [[Family 6 Model 47]]
 
|-
 
|-
 
| {{intel|Westmere EP|EP|l=core}}, {{intel|Gulftown|l=core}} || 0 || 0x6 || 0x2 || 0xC || [[Family 6 Model 44]]
 
| {{intel|Westmere EP|EP|l=core}}, {{intel|Gulftown|l=core}} || 0 || 0x6 || 0x2 || 0xC || [[Family 6 Model 44]]
 
|-
 
|-
−
| rowspan="3" | {{intel|Nehalem (Server)|l=arch}} || {{intel|Nehalem EX|EX|l=core}} || 0 || 0x6 || 0x2 || 0xE || [[Family 6 Model 46]]
+
| rowspan="3" | {{intel|Nehalem|Nehalem (Server)|l=arch}} || {{intel|Nehalem EX|EX|l=core}} || 0 || 0x6 || 0x2 || 0xE || [[Family 6 Model 46]]
 
|-
 
|-
 
| {{intel|Lynnfield|l=core}} || 0 || 0x6 || 0x1 || 0xE || [[Family 6 Model 30]]
 
| {{intel|Lynnfield|l=core}} || 0 || 0x6 || 0x1 || 0xE || [[Family 6 Model 30]]
Line 137: Line 250:
 
| {{intel|Nehalem EP|EP|l=core}}, {{intel|Nehalem WS|WS|l=core}}, <br>{{intel|Bloomfield|l=core}} || 0 || 0x6 || 0x1 || 0xA || [[Family 6 Model 26]]
 
| {{intel|Nehalem EP|EP|l=core}}, {{intel|Nehalem WS|WS|l=core}}, <br>{{intel|Bloomfield|l=core}} || 0 || 0x6 || 0x1 || 0xA || [[Family 6 Model 26]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Penryn (Server)|l=arch}} || {{intel|Dunnington|l=core}} || 0 || 0x6 || 0x1 || 0xD || [[Family 6 Model 29]]
+
| rowspan="2" | {{intel|Penryn|Penryn (Server)|l=arch}} || {{intel|Dunnington|l=core}} || 0 || 0x6 || 0x1 || 0xD || [[Family 6 Model 29]]
 
|-
 
|-
 
| {{intel|Harpertown|l=core}}, <br>{{intel|Penryn QC|l=core}}, <br>{{intel|Wolfdale|l=core}}, <br>{{intel|Yorkfield|l=core}} || 0 || 0x6 || 0x1 || 0x7 || [[Family 6 Model 23]]
 
| {{intel|Harpertown|l=core}}, <br>{{intel|Penryn QC|l=core}}, <br>{{intel|Wolfdale|l=core}}, <br>{{intel|Yorkfield|l=core}} || 0 || 0x6 || 0x1 || 0x7 || [[Family 6 Model 23]]
 
|-
 
|-
−
| {{intel|P6|l=arch}} ({{intel|Pentium}}) ||  || 0 || 0x6 || 0x0 || 0xA || [[Family 6 Model 10]]
+
| '''{{intel|P6|l=arch}}''' ({{intel|Pentium}}) ||  || 0 || 0x6 || 0x0 || 0xA || [[Family 6 Model 10]]
 
|-
 
|-
 
|}
 
|}
Line 147: Line 260:
 
==== [[Big Cores]] (Client) ====
 
==== [[Big Cores]] (Client) ====
 
Intel's client big cores refers to Intel mainstream SoCs that ship in most tablets, laptops, and desktop devices.
 
Intel's client big cores refers to Intel mainstream SoCs that ship in most tablets, laptops, and desktop devices.
−
+
<!--
−
{| class="wikitable"
+
* Panther Lake, Wildcat Lake, Nova Lake, and Razer Lake CPUs is underway. Titan Lake (2027 ?)
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
: LNL: Lunar Lake, PTL: Panther Lake, NVL: Nova Lake, WCL: Wildcat Lake, and RZL: Razer Lake.
 +
: M: Thin and Lightweight (Mobile), P: Performance (Mobile), H: Highest Performance (Mobile), S: Desktop.
 +
: Panther Lake in P and H variants, with varying TDPs. Previous leaks suggest a low-power U-version as well.
 +
 
 +
/* "Hybrid" Processors (P-Core/E-Core) */
 +
#define INTEL_PANTHERLAKE_L IFM(6, 0xCC) /* Cougar Cove / Crestmont ? */
 +
#define INTEL_LUNARLAKE_M IFM(6, 0xBD) /* Lion Cove / Skymont */
 +
#define INTEL_ARROWLAKE_H IFM(6, 0xC5) /* Lion Cove / Skymont */
 +
#define INTEL_ARROWLAKE IFM(6, 0xC6)
 +
#define INTEL_ARROWLAKE_U IFM(6, 0xB5)
 +
#define INTEL_METEORLAKE IFM(6, 0xAC) /* Redwood Cove / Crestmont */
 +
#define INTEL_METEORLAKE_L IFM(6, 0xAA)
 +
#define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
 +
#define INTEL_RAPTORLAKE_P IFM(6, 0xBA)
 +
#define INTEL_RAPTORLAKE_S IFM(6, 0xBF)
 +
#define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */
 +
#define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */
 +
#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
 +
-->
 +
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 +
|-
 +
| colspan="7" | • ''"Hybrid" Processors (P-[[Core]]/E-[[Core]])'' • [[Intel]] [[Core]] • [[Intel Atom]]
 
|-
 
|-
−
| {{intel|Razer Lake|l=arch}} ([[2027]]) || P, E || 0 || 0x6 || 0xC || 0xE ? || ?
+
! {{intel|Razer Lake|l=arch}} ([[2027]])  
 +
| Griffin Cove (P) <br>Golden Eagle (E) <br>• RZL-M/H || 0 || 0x6 || 0xC || 0x? || ?  
 
|- <!-- Coyote Cove P-cores and Arctic Wolf E-cores -->
 
|- <!-- Coyote Cove P-cores and Arctic Wolf E-cores -->
−
| {{intel|Nova Lake|l=arch}} ([[2026]]) || Coyote Cove P, <br>Arctic Wolf E || 0 || 0x6 || 0xC || 0xD ? || ?
+
! {{intel|Nova Lake|l=arch}} ([[2026]])  
−
|- <!-- Core Ultra; U/H, UL/HL; Cougar Cove (P-cores), Crestmont (E-cores and LP E-cores), Panther Cove (P-cores)
+
| Coyote Cove (P) <br>Arctic Wolf (E) <br>• NVL-S/H || 0 || 0x6 || 0xC || 0x? || ?  
−
Skymont or Darkmont (E-cores) ? -->
+
|- <!-- Wildcat Lake features next-gen Cougar Cove P-cores and Darkmont LPE-cores in a 2P+4LPE configuration -->
−
| {{intel|Panther Lake|l=arch}} ([[2025]]) || Cougar Cove P, <br>Crestmont E || 0 || 0x6 || 0xC || 0xC || [[Family 6 Model 204]] ? CC
+
! {{intel|Wildcat Lake|l=arch}} ([[2025]])  
−
|- <!-- Core Ultra 200V; Lion Cove P-cores and Skymont E-core -->
+
| {{intel|Cougar Cove|l=core}} (P) <br>{{intel|Darkmont|l=arch}} (LPE) <br>• WCL, 2P+4LPE || 0 || 0x6 || 0xC || 0xD ? || ?  
−
| {{intel|Lunar Lake|l=arch}} ([[2024]]) || Lion Cove P, <br>Skymont E || 0 || 0x6 || 0xB || 0xD || [[Family 6 Model 189]] ? BD
+
|- <!-- Core Ultra 300 ?; U/H, UL/HL; Cougar Cove (P-cores), Darkmont (E-cores and LP E-cores);
−
|- <!-- Core Ultra 2; Lion Cove P-cores and Skymont E-core -->
+
:(Panther Cove ? (P-cores), Skymont ? (E-cores)) • PTL-H P/H/U • 4P+8E+4LPE • Intel 18A • LGA2540 -->
−
| rowspan="3" | {{intel|Arrow Lake|l=arch}} ([[2024]]) || S || 0 || 0x6 || 0xC || 0x6 || [[Family 6 Model 198]] ? C6
+
! {{intel|Panther Lake|l=arch}} ([[2025]])  
 +
| {{intel|Cougar Cove|l=core}} (P) <br>{{intel|Darkmont|l=arch}} (E) <br>• PTL-U/H/P || 0 || 0x6 || 0xC || 0xC || [[Family 6 Model 204]]
 +
|- <!-- Bartlett Lake (Raptor Lake Refresh) • 8P+16E/12P+0E • LGA1700 • Intel 7
 +
:Raptor Lake-S, Raptor Lake-U, Raptor Lake-P, Raptor Lake-PX, Raptor Lake-H, Raptor Lake-HX -->
 +
! rowspan="3" | {{intel|Bartlett Lake|l=arch}} ([[2025]])<br><small>(Raptor Lake Refresh)</small>
 +
| {{intel|Raptor Cove|l=core}} (P) • U • H <hr>''{{intel|Gracemont|l=arch}}'' (E) • {{intel|Bartlett Lake N|BLL-N|l=core}} || 0 || 0x6 || 0xB || 0xF<hr>''0xE'' || [[Family 6 Model 191]] ?<hr>[[Family 6 Model 190]] ?
 
|-
 
|-
−
| Lion Cove P, <br>Skymont E || 0 || 0x6 || 0xC || 0x5 || [[Family 6 Model 197]] ? C5
+
| {{intel|Raptor Cove|l=core}} (P) • {{intel|Bartlett Lake P|BLL-P|l=core}} || 0 || 0x6 || 0xB || 0xA || [[Family 6 Model 186]]
 
|-
 
|-
−
| U || 0 || 0x6 || 0xB || 0x5 || [[Family 6 Model 181]] ? B5
+
| {{intel|Raptor Cove|l=core}} (P) • {{intel|Bartlett Lake S|BLL-S|l=core}} <br>Enhanced ''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0xB || 0x7 || [[Family 6 Model 183]]
 +
|- <!-- Core Ultra 200V; Lion Cove P-cores and Skymont E-core • 000B06D1 • 4C+4C Intel Core Ultra 9 288V @4200MHz (Lunar Lake-MX, Lion Cove + Skymont), top SKU -->
 +
! {{intel|Lunar Lake|l=arch}} ([[2024]])
 +
| • LNL-V • LNL-MX <hr>{{intel|Lion Cove|l=core}} (P) <br>{{intel|Skymont}} (E/LPE) || 0 || 0x6 || 0xB || 0xD<hr>0xC || [[Family 6 Model 189]] ? BD<hr>[[Family 6 Model 188]] ? BC
 +
|- <!-- Core Ultra 200U; Lion Cove P-cores and Skymont E-core • 2P+8E+2LPE • Intel 3 • LGA2049 -->
 +
! rowspan="3" | {{intel|Arrow Lake|l=arch}} ([[2024]])
 +
| • ARL-S || 0 || 0x6 || 0xC || 0x6 || [[Family 6 Model 198]] ? C6
 
|-
 
|-
−
| rowspan="2" | {{intel|Meteor Lake|l=arch}} ([[2023]]) || Redwood Cove P, <br>Crestmont E || 0 || 0x6 || 0xA || 0xC || [[Family 6 Model 172]] ? AC
+
| {{intel|Lion Cove|l=core}} (P) • ARL-H <br>{{intel|Skymont}} (E/LPE) || 0 || 0x6 || 0xC || 0x5 || [[Family 6 Model 197]] ? C5
 
|-
 
|-
−
| Redwood Cove P, <br>Crestmont E || 0 || 0x6 || 0xA || 0xA || [[Family 6 Model 170]] ? AA
+
| • ARL-U || 0 || 0x6 || 0xB || 0x5 || [[Family 6 Model 181]] ? B5
−
|- <!-- Raptor Lake-S, Raptor Lake-U, Raptor Lake-P, Raptor Lake-PX, Raptor Lake-H, Raptor Lake-HX -->
 
−
| rowspan="3" | {{intel|Raptor Lake|l=arch}} ([[2022]]) || Raptor Cove U, H ?<hr>''Gracemont'' E || 0 || 0x6 || 0xB || 0xF<hr>''0xE'' || [[Family 6 Model 191]] ?<hr>[[Family 6 Model 190]] ?
 
 
|-
 
|-
−
| Raptor Cove {{intel|Raptor Lake P|P|l=core}} || 0 || 0x6 || 0xB || 0xA || [[Family 6 Model 186]]
+
! rowspan="2" | {{intel|Meteor Lake|l=arch}} ([[2023]])
 +
| {{intel|Redwood Cove|l=core}} (P) <br>{{intel|Crestmont|l=arch}} (E) <br>• MTL-S || 0 || 0x6 || 0xA || 0xC || [[Family 6 Model 172]] ? AC
 
|-
 
|-
−
| Raptor Cove {{intel|Raptor Lake S|S|l=core}}, <br>''Gracemont'' E <!-- Enhanced ''Gracemont'' E --> || 0 || 0x6 || 0xB || 0x7 || [[Family 6 Model 183]]
+
| • MTL-N <br>{{intel|Crestmont|l=arch}} (E) || 0 || 0x6 || 0xA || 0xB<hr>0xA || [[Family 6 Model 171]] ? AB<hr>[[Family 6 Model 170]] ? AA
 +
|- <!-- Raptor Lake-S, Raptor Lake-U, Raptor Lake-P, Raptor Lake-PX, Raptor Lake-H, Raptor Lake-HX
 +
:RAPTORLAKE • IFM(6, 0xB7); RAPTORLAKE_P • IFM(6, 0xBA); RAPTORLAKE_S • IFM(6, 0xBF) ! -->
 +
! rowspan="3" | {{intel|Raptor Lake|l=arch}} ([[2022]])
 +
| {{intel|Raptor Cove|l=core}} (P) • U • H <hr>''{{intel|Gracemont|l=arch}}'' (E) • {{intel|Raptor Lake N|RPL-N|l=core}} || 0 || 0x6 || 0xB || 0xF<hr>''0xE'' || [[Family 6 Model 191]] ?<hr>[[Family 6 Model 190]] ?
 
|-
 
|-
−
| {{intel|Rocket Lake|l=arch}} ([[2021]]) || Cypress Cove {{intel|Rocket Lake S|S|l=core}} || 0 || 0x6 || 0xA || 0x7 || [[Family 6 Model 167]]
+
| {{intel|Raptor Cove|l=core}} (P) • {{intel|Raptor Lake P|RPL-P|l=core}} || 0 || 0x6 || 0xB || 0xA || [[Family 6 Model 186]]
−
|- <!-- 0xa5: Comet Lake-H/S, 0xa6: Comet Lake-U -->
+
|-
−
| rowspan="2" | {{intel|Comet Lake|l=arch}} ([[2020]]) || {{intel|Comet Lake U|U|l=core}} || 0 || 0x6 || 0xA || 0x6 || [[Family 6 Model 166]] ? <!-- 0x8/0xE • 142 ? -->
+
| {{intel|Raptor Cove|l=core}} (P) • {{intel|Raptor Lake S|RPL-S|l=core}} <br>Enhanced ''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0xB || 0x7 || [[Family 6 Model 183]]
 +
|-
 +
! rowspan="2" | {{intel|Alder Lake|l=arch}} ([[2021]])  
 +
| {{intel|Golden Cove|l=arch}} (P) • {{intel|Alder Lake P|ADL-P|l=core}} || 0 || 0x6 || 0x9 || 0xA || [[Family 6 Model 154]]
 +
|-
 +
| {{intel|Alder Lake S|l=core}} • {{intel|Alder Lake S|ADL-S|l=core}} <br>''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0x9 || 0x7 || [[Family 6 Model 151]]
 
|-
 
|-
−
| {{intel|Comet Lake S|S|l=core}}, {{intel|Comet Lake H|H|l=core}} || 0 || 0x6 || 0xA || 0x5 || [[Family 6 Model 165]]
+
| colspan="7" | • ''"Mono" Processors (P-[[Core]])'' •
 
|-
 
|-
−
| rowspan="2" | {{intel|Alder Lake|l=arch}} ([[2021]]) || {{intel|Golden Cove|l=arch}} {{intel|Alder Lake P|P|l=core}} || 0 || 0x6 || 0x9 || 0xA || [[Family 6 Model 154]]
+
! {{intel|Rocket Lake|l=arch}} ([[2021]])  
 +
| {{intel|Cypress Cove|l=arch}} (P) <br>• {{intel|Rocket Lake S|RKL-S|l=core}}, {{intel|Rocket Lake U|RKL-U|l=core}} || 0 || 0x6 || 0xA || 0x7 || [[Family 6 Model 167]]
 +
|- <!-- 0xa5: Comet Lake-H/S, 0xa6: Comet Lake-U -->
 +
! rowspan="2" | {{intel|Comet Lake|l=arch}} ([[2020]])
 +
| • {{intel|Comet Lake U|CML-U|l=core}} || 0 || 0x6 || 0xA || 0x6 || [[Family 6 Model 166]] ? <!-- 0x8/0xE • 142 ? -->
 
|-
 
|-
−
| {{intel|Alder Lake S|l=core}}, <br>''Gracemont'' E || 0 || 0x6 || 0x9 || 0x7 || [[Family 6 Model 151]]
+
| • {{intel|Comet Lake H|CML-H|l=core}} • {{intel|Comet Lake S|CML-S|l=core}} || 0 || 0x6 || 0xA || 0x5 || [[Family 6 Model 165]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Coffee Lake|l=arch}} || {{intel|Coffee Lake S|S|l=core}}, {{intel|Coffee Lake H|H|l=core}}, {{intel|Coffee Lake E|E|l=core}} || 0 || 0x6 || 0x9 || 0xE || [[Family 6 Model 158]]
+
! rowspan="2" | {{intel|Tiger Lake|l=arch}}  
 +
| • {{intel|Tiger Lake H|TGL-H|l=core}} (H35) || 0 || 0x6 || 0x8 || 0xD || [[Family 6 Model 141]]
 
|-
 
|-
−
| {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]]
+
| {{intel|Willow Cove|l=arch}} • {{intel|Tiger Lake U|TGL-U|l=core}} (UP) || 0 || 0x6 || 0x8 || 0xC || [[Family 6 Model 140]]
−
|- <!-- 0x8e: Kaby Lake mobile, 0x9e: Kaby Lake desktop -->
 
−
| rowspan="2" | {{intel|Kaby Lake|l=arch}} || {{intel|Kaby Lake DT|DT|l=core}}, {{intel|Kaby Lake H|H|l=core}}, {{intel|Kaby Lake S|S|l=core}}, {{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE || [[Family 6 Model 158]]
 
 
|-
 
|-
−
| {{intel|Kaby Lake Y|Y|l=core}}, {{intel|Kaby Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]]
+
! rowspan="2" | {{intel|Ice Lake (Client)|l=arch}}
 +
| {{intel|Sunny Cove|l=core}} • {{intel|Ice Lake U|ICL-U|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]] <!-- H/S/DT -->
 
|-
 
|-
−
| {{intel|Amber Lake|l=arch}} || {{intel|Amber Lake Y|Y|l=core}} || rowspan="2" | 0 || rowspan="2" | 0x6 || rowspan="2" | 0x8 || rowspan="2" | 0xE || rowspan="2" | [[Family 6 Model 142]]
+
| • {{intel|Ice Lake Y|ICL-Y|l=core}} || 0 || 0x6 || 0x7 || 0xD || [[Family 6 Model 125]] ?
 
|-
 
|-
−
| {{intel|Whiskey Lake|l=arch}} || {{intel|Whiskey Lake U|U|l=core}}  
+
! {{intel|Cannon Lake|l=arch}}  
 +
| {{intel|Palm Cove|l=arch}} • {{intel|Cannon Lake U|CNL-U|l=core}} (Y) || 0 || 0x6 || 0x6 || 0x6 || [[Family 6 Model 102]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Tiger Lake|l=arch}} || {{intel|Tiger Lake H|H|l=core}} || 0 || 0x6 || 0x8 || 0xD || [[Family 6 Model 141]]
+
! rowspan="2" | {{intel|Coffee Lake|l=arch}}  
 +
| • {{intel|Coffee Lake H|CFL-H|l=core}} • {{intel|Coffee Lake S|CFL-S|l=core}} • {{intel|Coffee Lake E|CFL-E|l=core}} || 0 || 0x6 || 0x9 || 0xE || [[Family 6 Model 158]] <!--  (Stepping 10-13) -->
 
|-
 
|-
−
| {{intel|Tiger Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xC || [[Family 6 Model 140]]
+
| • {{intel|Coffee Lake U|CFL-U|l=core}} (R) (Stepping 10) || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]]
 +
|- <!-- 0x8e: Kaby Lake mobile, 0x9e: Kaby Lake desktop -->
 +
! rowspan="2" | {{intel|Kaby Lake|l=arch}}
 +
|  • {{intel|Kaby Lake DT|KBL-DT|l=core}} • {{intel|Kaby Lake X|KBL-X|l=core}} <hr>• {{intel|Kaby Lake H|KBL-H|l=core}} • {{intel|Kaby Lake S|KBL-S|l=core}} (G) || 0 || 0x6 || 0x9 || 0xE || [[Family 6 Model 158]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Ice Lake (Client)|l=arch}} || {{intel|Ice Lake U|U|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]]
+
| • {{intel|Kaby Lake Y|KBL-Y|l=core}} • {{intel|Kaby Lake U|KBL-U|l=core}} (R) || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]]
 
|-
 
|-
−
| {{intel|Ice Lake Y|Y|l=core}} || 0 || 0x6 || 0x7 || 0xD || [[Family 6 Model 125]] ?
+
! {{intel|Amber Lake|l=arch}}
 +
| • {{intel|Amber Lake Y|AML-Y|l=core}} (Stepping 9) || rowspan="2" | 0 || rowspan="2" | 0x6 || rowspan="2" | 0x8 || rowspan="2" | 0xE || rowspan="2" | [[Family 6 Model 142]]
 
|-
 
|-
−
| {{intel|Cannon Lake|l=arch}} || {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 || [[Family 6 Model 102]]
+
! {{intel|Whiskey Lake|l=arch}}  
−
|- <!-- Skylake: 0x4e: Skylake mobile, 0x5e: Skylake desktop -->
+
| • {{intel|Whiskey Lake U|WHL-U|l=core}} (Stepping 11/12)
−
| rowspan="2" | {{intel|Skylake (Client)|l=arch}} || {{intel|Skylake DT|DT|l=core}}, {{intel|Skylake H|H|l=core}}, {{intel|Skylake S|S|l=core}} || 0 || 0x6 || 0x5 || 0xE || [[Family 6 Model 94]]
+
|- <!-- Skylake: 0x4e: Skylake Mobile, 0x5e: Skylake Desktop -->
 +
! rowspan="2" | {{intel|Skylake (Client)|l=arch}}  
 +
| • {{intel|Skylake H|SKL-H|l=core}} • {{intel|Skylake S|SKL-S|l=core}} • {{intel|Skylake DT|SKL-DT|l=core}} || 0 || 0x6 || 0x5 || 0xE || [[Family 6 Model 94]]
 
|-
 
|-
−
| {{intel|Skylake Y|Y|l=core}}, {{intel|Skylake U|U|l=core}} || 0 || 0x6 || 0x4 || 0xE || [[Family 6 Model 78]]
+
| • {{intel|Skylake Y|SKL-Y|l=core}} • {{intel|Skylake U|SKL-U|l=core}} || 0 || 0x6 || 0x4 || 0xE || [[Family 6 Model 78]]
 
|- <!-- Broadwell: Client: 0x3d, 0x47, Server: 0x4f ?, 0x56 ? -->
 
|- <!-- Broadwell: Client: 0x3d, 0x47, Server: 0x4f ?, 0x56 ? -->
−
| rowspan="3" | {{intel|Broadwell (Client)|l=arch}} || {{intel|Broadwell C|C|l=core}}, {{intel|Broadwell W|W|l=core}} || 0 || 0x6 || 0x4 || 0x7 || [[Family 6 Model 71]]
+
! rowspan="2" | {{intel|Broadwell (Client)|l=arch}}  
−
|-
+
| • {{intel|Broadwell H|BDW-H|l=core}} • {{intel|Broadwell C|BDW-C|l=core}} • {{intel|Broadwell W|BDW-W|l=core}} || 0 || 0x6 || 0x4 || 0x7 || [[Family 6 Model 71]]
−
| {{intel|Broadwell U|U|l=core}}, {{intel|Broadwell Y|Y|l=core}}, {{intel|Broadwell S|S|l=core}} || 0 || 0x6 || 0x3 || 0xD || [[Family 6 Model 61]]
 
 
|-
 
|-
−
| {{intel|Broadwell H|H|l=core}} || 0 || 0x6 || 0x4 || 0x7 || [[Family 6 Model 71]]
+
| • {{intel|Broadwell Y|BDW-Y|l=core}} • {{intel|Broadwell U|BDW-U|l=core}} • {{intel|Broadwell S|BDW-S|l=core}} || 0 || 0x6 || 0x3 || 0xD || [[Family 6 Model 61]]
 
|- <!-- Haswell: Client: 0x3c, 0x45, 0x46; Server: 0x3f ? -->
 
|- <!-- Haswell: Client: 0x3c, 0x45, 0x46; Server: 0x3f ? -->
−
| rowspan="3" | {{intel|Haswell (Client)|l=arch}} || {{intel|Haswell GT3E|GT3E|l=core}} || 0 || 0x6 || 0x4 || 0x6 || [[Family 6 Model 70]]
+
! rowspan="3" | {{intel|Haswell (Client)|l=arch}}  
 +
| • {{intel|Haswell MB|HSW-MB|l=core}} (GT3E) || 0 || 0x6 || 0x4 || 0x6 || [[Family 6 Model 70]]
 
|-
 
|-
−
| {{intel|Haswell ULT|ULT|l=core}} || 0 || 0x6 || 0x4 || 0x5 || [[Family 6 Model 69]]
+
| • {{intel|Haswell U|HSW-U|l=core}} (ULT/ULX/Y) || 0 || 0x6 || 0x4 || 0x5 || [[Family 6 Model 69]]
 
|-
 
|-
−
| {{intel|Haswell S|S|l=core}} || 0 || 0x6 || 0x3 || 0xC || [[Family 6 Model 60]]
+
| • {{intel|Haswell S|HSW-S|l=core}} (H/DT) || 0 || 0x6 || 0x3 || 0xC || [[Family 6 Model 60]]
 
|-
 
|-
−
| {{intel|Ivy Bridge (Client)|l=arch}} || {{intel|Ivy Bridge M|M|l=core}}, {{intel|Ivy Bridge H|H|l=core}}, <br>{{intel|Gladden|l=core}} || 0 || 0x6 || 0x3 || 0xA || [[Family 6 Model 58]]
+
! {{intel|Ivy Bridge (Client)|l=arch}}  
 +
| • {{intel|Ivy Bridge M|IVB-M|l=core}} • {{intel|Ivy Bridge H|IVB-H|l=core}} ({{intel|Gladden|l=core}}) || 0 || 0x6 || 0x3 || 0xA || [[Family 6 Model 58]]
 
|-
 
|-
−
| {{intel|Sandy Bridge (Client)|l=arch}} || {{intel|Sandy Bridge M|M|l=core}}, {{intel|Sandy Bridge H|H|l=core}}, <br>{{intel|Sandy Bridge Celeron|Celeron|l=celeron}} || 0 || 0x6 || 0x2 || 0xA || [[Family 6 Model 42]]
+
! {{intel|Sandy Bridge (Client)|l=arch}}  
 +
| • {{intel|Sandy Bridge M|SNB-M|l=core}} • {{intel|Sandy Bridge H|SNB-H|l=core}} ({{intel|Celeron|l=celeron}}) || 0 || 0x6 || 0x2 || 0xA || [[Family 6 Model 42]]
 
|-
 
|-
−
| {{intel|Westmere (Client)|l=arch}} || {{intel|Arrandale|l=core}}, <br>{{intel|Clarkdale|l=core}} || 0 || 0x6 || 0x2 || 0x5 || [[Family 6 Model 37]]
+
! {{intel|Westmere (Client)|l=arch}}  
 +
| {{intel|Arrandale|l=core}}, {{intel|Clarkdale|l=core}} || 0 || 0x6 || 0x2 || 0x5 || [[Family 6 Model 37]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Nehalem (Client)|l=arch}} || <s>{{intel|Auburndale|l=core}}</s>, <br><s>{{intel|Havendale|l=core}}</s> || 0 || 0x6 || 0x1 ||0xF || [[Family 6 Model 31]]
+
! rowspan="2" | {{intel|Nehalem (Client)|l=arch}}  
 +
| <s>{{intel|Auburndale|l=core}}</s>, <s>{{intel|Havendale|l=core}}</s> || 0 || 0x6 || 0x1 ||0xF || [[Family 6 Model 31]]
 
|-
 
|-
 
| {{intel|Clarksfield|l=core}} || 0 || 0x6 || 0x1 || 0xE || [[Family 6 Model 30]]
 
| {{intel|Clarksfield|l=core}} || 0 || 0x6 || 0x1 || 0xE || [[Family 6 Model 30]]
 
|-
 
|-
−
| {{intel|Penryn (Client)|l=arch}} || {{intel|Penryn|l=core}}, <br>{{intel|Wolfdale|l=core}}, <br>{{intel|Yorkfield|l=core}} || 0 || 0x6 || 0x1 || 0x7 || [[Family 6 Model 23]]
+
! {{intel|Penryn (Client)|l=arch}}  
 +
| {{intel|Penryn|l=arch}}, {{intel|Wolfdale|l=core}}, {{intel|Yorkfield|l=core}} || 0 || 0x6 || 0x1 || 0x7 || [[Family 6 Model 23]]
 
|-
 
|-
−
| rowspan="2" | {{intel|Core (Client)|l=arch}} || {{intel|Merom L|l=core}} || 0 || 0x6 || 0x1 ||  0x6 || [[Family 6 Model 22]]
+
! rowspan="2" | {{intel|Core (Client)|l=arch}}  
 +
| {{intel|Merom L|l=core}} || 0 || 0x6 || 0x1 ||  0x6 || [[Family 6 Model 22]]
 
|-
 
|-
 
| {{intel|Merom|l=core}} || 0 || 0x6 || 0x0 || 0xF || [[Family 6 Model 15]]
 
| {{intel|Merom|l=core}} || 0 || 0x6 || 0x0 || 0xF || [[Family 6 Model 15]]
 
|-
 
|-
−
| {{intel|Modified Pentium M|l=arch}} || {{intel|Yonah|l=core}} || 0 || 0x6 || 0x0 || 0xE || [[Family 6 Model 14]]
+
! {{intel|Modified Pentium M|l=arch}}  
 +
| {{intel|Yonah|l=core}} || 0 || 0x6 || 0x0 || 0xE || [[Family 6 Model 14]]
 
|-
 
|-
−
| rowspan="3" | {{intel|Pentium M|l=arch}} || {{intel|Tolapai|l=core}} || 0 || 0x6 || 0x1 || 0x5 || [[Family 6 Model 21]]
+
! rowspan="3" | {{intel|Pentium M|l=arch}}  
 +
| {{intel|Tolapai|l=core}} || 0 || 0x6 || 0x1 || 0x5 || [[Family 6 Model 21]]
 
|-
 
|-
 
| {{intel|Dothan|l=core}} || 0 || 0x6 || 0x0 || 0xD || [[Family 6 Model 13]]
 
| {{intel|Dothan|l=core}} || 0 || 0x6 || 0x0 || 0xD || [[Family 6 Model 13]]
Line 248: Line 423:
 
| {{intel|Banias|l=core}} || 0 || 0x6 || 0x0 || 0x9 || [[Family 6 Model 9]]
 
| {{intel|Banias|l=core}} || 0 || 0x6 || 0x0 || 0x9 || [[Family 6 Model 9]]
 
|-
 
|-
−
| rowspan="7" | {{intel|P6|l=arch}} ({{intel|Pentium}}) || {{intel|Tualatin|l=core}} || 0 || 0x6 || 0x0 || 0xB || [[Family 6 Model 11]]
+
! rowspan="7" | {{intel|P6|l=arch}} ({{intel|Pentium}})  
 +
| {{intel|Tualatin|l=core}} ([[Pentium]] III) || 0 || 0x6 || 0x0 || 0xB || [[Family 6 Model 11]]
 
|-
 
|-
−
| {{intel|Coppermine|l=core}}, <br>{{intel|Coppermine T|l=core}} || 0 || 0x6 || 0x0 || 0x8 || [[Family 6 Model 8]]
+
| {{intel|Coppermine|l=core}}, {{intel|Coppermine T|l=core}} || 0 || 0x6 || 0x0 || 0x8 || [[Family 6 Model 8]]
 
|-
 
|-
 
| {{intel|Katmai|l=core}} || 0 || 0x6 || 0x0 || 0x7 || [[Family 6 Model 7]]
 
| {{intel|Katmai|l=core}} || 0 || 0x6 || 0x0 || 0x7 || [[Family 6 Model 7]]
Line 256: Line 432:
 
| || 0 || 0x6 || 0x0 || 0x6 || [[Family 6 Model 6]]
 
| || 0 || 0x6 || 0x0 || 0x6 || [[Family 6 Model 6]]
 
|-
 
|-
−
| || 0 || 0x6 || 0x0 || 0x5 || [[Family 6 Model 5]]
+
| {{intel|Deschutes|l=core}} ([[Pentium]] III) || 0 || 0x6 || 0x0 || 0x5 || [[Family 6 Model 5]]
 
|-
 
|-
−
| || 0 || 0x6 || 0x0 || 0x3 || [[Family 6 Model 3]]
+
| {{intel|Klamath|l=core}} ([[Pentium]] II) || 0 || 0x6 || 0x0 || 0x3 || [[Family 6 Model 3]]
 
|-
 
|-
−
| || 0 || 0x6 || 0x0 || 0x1 || [[Family 6 Model 1]]
+
| [[Pentium]] Pro || 0 || 0x6 || 0x0 || 0x1 || [[Family 6 Model 1]]
 
|-
 
|-
 
|}
 
|}
 +
<!--
 +
#define INTEL_PENTIUM_PRO IFM(6, 0x01)
 +
#define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03)
 +
#define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05)
 +
#define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B)
 +
#define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D)
 +
 +
#define INTEL_CORE_YONAH IFM(6, 0x0E)
 +
 +
#define INTEL_CORE2_MEROM IFM(6, 0x0F)
 +
#define INTEL_CORE2_MEROM_L IFM(6, 0x16)
 +
#define INTEL_CORE2_PENRYN IFM(6, 0x17)
 +
#define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D)
 +
 +
#define INTEL_NEHALEM IFM(6, 0x1E)
 +
#define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */
 +
#define INTEL_NEHALEM_EP IFM(6, 0x1A)
 +
#define INTEL_NEHALEM_EX IFM(6, 0x2E)
 +
 +
#define INTEL_WESTMERE IFM(6, 0x25)
 +
#define INTEL_WESTMERE_EP IFM(6, 0x2C)
 +
#define INTEL_WESTMERE_EX IFM(6, 0x2F)
 +
 +
#define INTEL_SANDYBRIDGE IFM(6, 0x2A)
 +
#define INTEL_SANDYBRIDGE_X IFM(6, 0x2D)
 +
#define INTEL_IVYBRIDGE IFM(6, 0x3A)
 +
#define INTEL_IVYBRIDGE_X IFM(6, 0x3E)
 +
 +
#define INTEL_HASWELL IFM(6, 0x3C)
 +
#define INTEL_HASWELL_X IFM(6, 0x3F)
 +
#define INTEL_HASWELL_L IFM(6, 0x45)
 +
#define INTEL_HASWELL_G IFM(6, 0x46)
 +
 +
#define INTEL_BROADWELL IFM(6, 0x3D)
 +
#define INTEL_BROADWELL_G IFM(6, 0x47)
 +
#define INTEL_BROADWELL_X IFM(6, 0x4F)
 +
#define INTEL_BROADWELL_D IFM(6, 0x56)
 +
 +
#define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */
 +
#define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */
 +
#define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */
 +
/*                CASCADELAKE_X 0x55   Sky Lake -- s: 7    */
 +
/*                COOPERLAKE_X 0x55   Sky Lake -- s: 11    */
 +
 +
#define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */
 +
/*                AMBERLAKE_L 0x8E   Sky Lake -- s: 9    */
 +
/*                COFFEELAKE_L 0x8E   Sky Lake -- s: 10    */
 +
/*                WHISKEYLAKE_L 0x8E      Sky Lake -- s: 11,12 */
 +
 +
#define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */
 +
/*                COFFEELAKE 0x9E   Sky Lake -- s: 10-13 */
 +
 +
#define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */
 +
#define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */
 +
 +
#define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */
 +
 +
#define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */
 +
#define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */
 +
#define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */
 +
#define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */
 +
#define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */
 +
 +
#define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */
 +
 +
#define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */
 +
#define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */
 +
 +
#define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */
 +
 +
#define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) /* Raptor Cove */
 +
 +
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */
 +
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
 +
-->
  
 
=== Family 5 ===
 
=== Family 5 ===
−
{| class="wikitable"
+
 
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
|-
 +
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 
|-
 
|-
−
| rowspan="2" | {{intel|Lakemont|l=arch}} <br>([[Lake]]) || rowspan="2" | {{intel|Quark}} <br>(X1000, D1000) || 0 || 0x5 || 0x0 || 0xA || [[Family 5 Model 10]]
+
! rowspan="2" | {{intel|Lakemont|l=arch}} <br>([[Lake]])  
 +
| {{intel|Quark}} D1000 || 0 || 0x5 || 0x0 || 0xA || [[Family 5 Model 10]]
 
|-
 
|-
−
| 0 || 0x5 || 0x0 || 0x9 || [[Family 5 Model 9]]
+
| {{intel|Quark}} X1000 || 0 || 0x5 || 0x0 || 0x9 || [[Family 5 Model 9]]
 
|-
 
|-
−
| rowspan="5" | {{intel|P5|l=arch}} ([[1993]]) <br>• {{intel|Pentium}} || rowspan="2" | P55C (Mobile) || 0 || 0x5 || 0x0 || 0x8 || [[Family 5 Model 8]]
+
! rowspan="6" | {{intel|P5|l=arch}} ([[1993]]) <br>• {{intel|Pentium}}  
 +
| rowspan="2" | P55C (Mobile) || 0 || 0x5 || 0x0 || 0x8 || [[Family 5 Model 8]]
 
|-
 
|-
 
| 0 || 0x5 || 0x0 || 0x7 || [[Family 5 Model 7]]
 
| 0 || 0x5 || 0x0 || 0x7 || [[Family 5 Model 7]]
 
|-
 
|-
−
| P55C || 0 || 0x5 || 0x0 || 0x4 || [[Family 5 Model 4]]
+
| P55C ([[Pentium]] MMX) || 0 || 0x5 || 0x0 || 0x4 || [[Family 5 Model 4]]
 
|-
 
|-
−
| P54CS || 0 || 0x5 || 0x0 || 0x2 || [[Family 5 Model 2]]
+
| P54CS ([[Pentium]] 75) || 0 || 0x5 || 0x0 || 0x2 || [[Family 5 Model 2]]
 +
|-
 +
| P54, P54CQS || 0 || 0x5 || 0x0 || 0x1 || [[Family 5 Model 1]]
 +
|-
 +
| P5 (A-step) || 0 || 0x5 || 0x0 || 0x0 || [[Family 5 Model 0]]
 
|-
 
|-
−
| P5, P54, P54CQS || 0 || 0x5 || 0x0 || 0x1 || [[Family 5 Model 1]]
 
 
|}
 
|}
 +
<!--
 +
/* Family 5 */
 +
#define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */
 +
#define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C */
 +
#define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */
 +
#define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */
 +
-->
  
 
=== Family 4 ===
 
=== Family 4 ===
−
{| class="wikitable"
+
 
−
! Microarchitecture !! Core !! Extended Family !! Family !! Extended Model !! Model !! Family • Model  
+
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 70%; text-align:center;"
 +
|-
 +
! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model  
 
|-
 
|-
−
| rowspan="8" | {{intel|80486|l=arch}} || || 0 || 0x4 || 0x0 || 0x9 || [[Family 4 Model 9]]
+
! rowspan="8" | [[Intel]] {{intel|80486|486|l=arch}} <br>({{intel|80486|l=arch}})
 +
| [[Intel]] {{intel|80486}} || 0 || 0x4 || 0x0 || 0x9 || [[Family 4 Model 9]]
 
|-
 
|-
−
| {{intel|80486 DX4|80486DX4}} || 0 || 0x4 || 0x0 || 0x8 || [[Family 4 Model 8]]
+
| [[Intel]] {{intel|80486 DX4|486DX4}}  
 +
| 0 || 0x4 || 0x0 || 0x8 || [[Family 4 Model 8]]
 
|-
 
|-
−
| || 0 || 0x4 || 0x0 || 0x7 || [[Family 4 Model 7]]
+
| [[Intel]] {{intel|80486}} || 0 || 0x4 || 0x0 || 0x7 || [[Family 4 Model 7]]
 
|-
 
|-
−
| || 0 || 0x4 || 0x0 || 0x5 || [[Family 4 Model 5]]
+
| [[Intel]] {{intel|80486}} || 0 || 0x4 || 0x0 || 0x5 || [[Family 4 Model 5]]
 
|-
 
|-
−
| {{intel|80486#i486SL|80486SL}} || 0 || 0x4 || 0x0 || 0x4 || [[Family 4 Model 4]]
+
| [[Intel]] {{intel|80486#i486SL|486SL}} || 0 || 0x4 || 0x0 || 0x4 || [[Family 4 Model 4]]
 
|-
 
|-
−
| {{intel|80486 DX2|80486DX2}} || 0 || 0x4 || 0x0 || 0x3 || [[Family 4 Model 3]]
+
| [[Intel]] {{intel|80486 DX2|486DX2}} || 0 || 0x4 || 0x0 || 0x3 || [[Family 4 Model 3]]
 
|-
 
|-
−
| {{intel|80486#i486SX|80486SX}} || 0 || 0x4 || 0x0 || 0x2 || [[Family 4 Model 2]]
+
| [[Intel]] {{intel|80486#i486SX|486SX}} || 0 || 0x4 || 0x0 || 0x2 || [[Family 4 Model 2]]
 
|-
 
|-
−
| {{intel|80486#i486DX|80486DX}} || 0 || 0x4 || 0x0 || 0x1 || [[Family 4 Model 1]]
+
| [[Intel]] {{intel|80486#i486DX|486DX}} || 0 || 0x4 || 0x0 || 0x1 || [[Family 4 Model 1]]
 
|-
 
|-
 
|}
 
|}

Latest revision as of 20:18, 2 July 2025

x86
Instruction Set Architecture
General
Variants
Topics
CPUIDs
Modes
Extensions(all)
v · d · e

Below is a list of Intel's CPUID broken down by their respective core names and microarchitecture:

CPUIDs[edit]

Family 19[edit]

Microarchitecture Core Platform Extended
Family 		Family Extended
Model 		Model Family • Model
Diamond Rapids
(2025) 		Panther Cove X (P) • 18A
DMR-AP/SP (LGA9324) 		Mountain
Stream 		0x4 0xF 0x0 0x1 Family 19 Model 1
Nova Lake
(2026) 		Coyote Cove (P) • 18A
Arctic Wolf (E) • NVL-S/H 		0x4 0xF 0x0 0x0 Family 19 Model 0

Key changes from Granite Rapids:

• Core: Redwood Cove+ → Panther Cove X (P-core), Platform: Eagle Stream → Mountain Stream

Family 15[edit]

• Intel • Core • Xeon
Microarchitecture Core Fab node Extended
Family 		Family Extended
Model 		Model Family • Model
Modified Pentium M
(2006) 		Cedar Mill (2C)
(Xeon Dempsey) 		65 nm 0 0xF 0x0 0x6 Family 15 Model 6
Netburst (P68)
(2000) 		Prescott (2M) 90 nm 0 0xF 0x0 0x4 Family 15 Model 4
Prescott 90 nm 0 0xF 0x0 0x3 Family 15 Model 3
Northwood 130 nm 0 0xF 0x0 0x2 Family 15 Model 2
Willamette
(Xeon Foster) 		180 nm 0 0xF 0x0 0x1 Family 15 Model 1

Family 11[edit]

Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
Knights Corner (2011) 62 cores (22 nm) 0 0xB 0x0 0x1 Family 11 Model 1
Knights Ferry (2010) 32 cores (45 nm) 0 0xB 0x0 0x0 Family 11 Model 0

Family 6[edit]

MIC Architecture[edit]

• Xeon Phi •
Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
Knights Mill
Knights Hill,
Knights Peak 		Xeon Phi
64C/256T
14 nm 		0 0x6 0x8 0x5 Family 6 Model 133
Knights Landing Xeon Phi
72C/288T
14 nm 		0 0x6 0x5 0x7 Family 6 Model 87

Small Cores[edit]

Intel's client small cores refers to Intel low-power SoCs that ship in low power

laptops, tablets, embedded devices, and low-power servers.
• "Small Cores" Processors (Atom/E-Core) •
Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
Darkmont
(2025) 		Clearwater Forest
CWF-AP/CWF-SP
Wildcat Lake WCL
Panther Lake U/H/P 		0 0x6 .
0xD
0x?
0xC 		.
0xD
0x?
0xC 		Darkmont_X
IFM (6, 0xDD)
.
.
Skymont
(2024) 		Arrow Lake S/U
Lunar Lake MX/V 		0 0x6 0xB
0xB 		0x5
0xC 		0xB 0x5, 0xC 0x5/0x6
0xB 0xC/0xD
Crestmont
(2023) 		Sierra Forest SP
Meteor Lake S/N
Grand Ridge 		0 0x6 0xA
0xA
0xB 		0xF
0xA
0x6 		IFM (6, 0xAF)
0xA, 0xB, 0xC
IFM (6, 0xB6)
Gracemont
(2021) 		Alder Lake N
Raptor Lake S/N
Twin Lake S 		0 0x6 0xB
0xB
0x? 		0xE
0x7
0x? 		IFM (6, 0xBE)
0xB 0x7/0xB 0xE
?
Tremont
(2020) 		Jasper Lake (L) 0 0x6 0x9 0xC Family 6 Model 156
Elkhart Lake 0 0x6 0x9 0x6 Family 6 Model 150
Jacobsville (D) 0 0x6 0x8 0x6 IFM (6, 0x86)
Lakefield 0 0x6 0x8 0xA Family 6 Model 138
Goldmont Plus Gemini Lake 0 0x6 0x7 0xA Family 6 Model 122
Goldmont Denverton (D) 0 0x6 0x5 0xF Family 6 Model 95
Apollo Lake,
Broxton,
Willow Trail 		0 0x6 0x5 0xC Family 6 Model 92
Airmont Cherry Trail,
Braswell 		0 0x6 0x4 0xC Family 6 Model 76
Lightning
Mountain (NP) 		0 0x6 0x7 0x5 IFM (6, 0x75)
Silvermont SoFIA 0 0x6 0x5 0xD Family 6 Model 93
Anniedale (MID2) 0 0x6 0x5 0xA Family 6 Model 90
Avoton,
Rangeley (D) 		0 0x6 0x4 0xD Family 6 Model 77
Merriefield,
Tangier (MID) 		0 0x6 0x4 0xA Family 6 Model 74
Bay Trail,
Valleyview 		0 0x6 0x3 0x7 Family 6 Model 55
Saltwell Cedarview 0 0x6 0x3 0x6 Family 6 Model 54
Cloverview (TAB) 0 0x6 0x3 0x5 Family 6 Model 53
Penwell (MID) 0 0x6 0x2 0x7 Family 6 Model 39
Bonnell Silverthorne,
Lincroft (MID) 		0 0x6 0x2 0x6 Family 6 Model 38
Diamondville,
Pineview 		0 0x6 0x1 0xC Family 6 Model 28

Big Cores (Server)[edit]

Intel's server big cores refers to Intel workstation and data center SoCs that ship

in most enterprise desktops, workstations, and servers.
Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
Clearwater Forest
(2025) 		CWF-AP (LGA7529)
Darkmont (E) • 18A
CWF-SP (LGA4710) 		0 0x6 0xD 0xD Family 6 Model 221
Sierra Forest
(2024) 		Crestmont (E) SP
SRF-SP 		0 0x6 0xA 0xF Family 6 Model 175
Granite Rapids
(2024) 		Redwood Cove (D) 0 0x6 0xA 0xE Family 6 Model 174
Redwood Cove 0 0x6 0xA 0xD Family 6 Model 173
Emerald Rapids
(2023) 		Golden Cove 0 0x6 0xC 0xF Family 6 Model 207
Sapphire Rapids
(2023) 		Golden Cove SP 0 0x6 0x8 0xF Family 6 Model 143
Ice Lake (Server) DE 0 0x6 0x6 0xC Family 6 Model 108
SP 0 0x6 0x6 0xA Family 6 Model 106
Cooper Lake (stepping 11)  ? 0 0x6 0x5 0x5 Family 6 Model 85
Cascade Lake (stepping 5-7) SP, X, W
Skylake (Server) SP, X, DE, W
Broadwell (Server) DE, Hewitt Lake 0 0x6 0x5 0x6 Family 6 Model 86
E, EP, EX 0 0x6 0x4 0xF Family 6 Model 79
Haswell (Server) E, EP, EX 0 0x6 0x3 0xF Family 6 Model 63
Ivy Bridge (Server) E, EN, EP, EX 0 0x6 0x3 0xE Family 6 Model 62
Sandy Bridge (Server) E, EN, EP 0 0x6 0x2 0xD Family 6 Model 45
Westmere (Server) EX 0 0x6 0x2 0xF Family 6 Model 47
EP, Gulftown 0 0x6 0x2 0xC Family 6 Model 44
Nehalem (Server) EX 0 0x6 0x2 0xE Family 6 Model 46
Lynnfield 0 0x6 0x1 0xE Family 6 Model 30
EP, WS,
Bloomfield 		0 0x6 0x1 0xA Family 6 Model 26
Penryn (Server) Dunnington 0 0x6 0x1 0xD Family 6 Model 29
Harpertown,
Penryn QC,
Wolfdale,
Yorkfield 		0 0x6 0x1 0x7 Family 6 Model 23
P6 (Pentium) 0 0x6 0x0 0xA Family 6 Model 10

Big Cores (Client)[edit]

Intel's client big cores refers to Intel mainstream SoCs that ship in most tablets, laptops, and desktop devices.

Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
• "Hybrid" Processors (P-Core/E-Core) • Intel Core • Intel Atom
Razer Lake (2027) Griffin Cove (P)
Golden Eagle (E)
• RZL-M/H 		0 0x6 0xC 0x?  ?
Nova Lake (2026) Coyote Cove (P)
Arctic Wolf (E)
• NVL-S/H 		0 0x6 0xC 0x?  ?
Wildcat Lake (2025) Cougar Cove (P)
Darkmont (LPE)
• WCL, 2P+4LPE 		0 0x6 0xC 0xD ?  ?
Panther Lake (2025) Cougar Cove (P)
Darkmont (E)
• PTL-U/H/P 		0 0x6 0xC 0xC Family 6 Model 204
Bartlett Lake (2025)
(Raptor Lake Refresh) 		Raptor Cove (P) • U • H
Gracemont (E) • BLL-N 		0 0x6 0xB 0xF
0xE 		Family 6 Model 191 ?
Family 6 Model 190 ?
Raptor Cove (P) • BLL-P 0 0x6 0xB 0xA Family 6 Model 186
Raptor Cove (P) • BLL-S
Enhanced Gracemont (E) 		0 0x6 0xB 0x7 Family 6 Model 183
Lunar Lake (2024) • LNL-V • LNL-MX
Lion Cove (P)
Skymont (E/LPE) 		0 0x6 0xB 0xD
0xC 		Family 6 Model 189 ? BD
Family 6 Model 188 ? BC
Arrow Lake (2024) • ARL-S 0 0x6 0xC 0x6 Family 6 Model 198 ? C6
Lion Cove (P) • ARL-H
Skymont (E/LPE) 		0 0x6 0xC 0x5 Family 6 Model 197 ? C5
• ARL-U 0 0x6 0xB 0x5 Family 6 Model 181 ? B5
Meteor Lake (2023) Redwood Cove (P)
Crestmont (E)
• MTL-S 		0 0x6 0xA 0xC Family 6 Model 172 ? AC
• MTL-N
Crestmont (E) 		0 0x6 0xA 0xB
0xA 		Family 6 Model 171 ? AB
Family 6 Model 170 ? AA
Raptor Lake (2022) Raptor Cove (P) • U • H
Gracemont (E) • RPL-N 		0 0x6 0xB 0xF
0xE 		Family 6 Model 191 ?
Family 6 Model 190 ?
Raptor Cove (P) • RPL-P 0 0x6 0xB 0xA Family 6 Model 186
Raptor Cove (P) • RPL-S
Enhanced Gracemont (E) 		0 0x6 0xB 0x7 Family 6 Model 183
Alder Lake (2021) Golden Cove (P) • ADL-P 0 0x6 0x9 0xA Family 6 Model 154
Alder Lake S • ADL-S
Gracemont (E) 		0 0x6 0x9 0x7 Family 6 Model 151
• "Mono" Processors (P-Core) •
Rocket Lake (2021) Cypress Cove (P)
• RKL-S, RKL-U 		0 0x6 0xA 0x7 Family 6 Model 167
Comet Lake (2020) • CML-U 0 0x6 0xA 0x6 Family 6 Model 166 ?
• CML-H • CML-S 0 0x6 0xA 0x5 Family 6 Model 165
Tiger Lake • TGL-H (H35) 0 0x6 0x8 0xD Family 6 Model 141
Willow Cove • TGL-U (UP) 0 0x6 0x8 0xC Family 6 Model 140
Ice Lake (Client) Sunny Cove • ICL-U 0 0x6 0x7 0xE Family 6 Model 126
• ICL-Y 0 0x6 0x7 0xD Family 6 Model 125 ?
Cannon Lake Palm Cove • CNL-U (Y) 0 0x6 0x6 0x6 Family 6 Model 102
Coffee Lake • CFL-H • CFL-S • CFL-E 0 0x6 0x9 0xE Family 6 Model 158
• CFL-U (R) (Stepping 10) 0 0x6 0x8 0xE Family 6 Model 142
Kaby Lake • KBL-DT • KBL-X
• KBL-H • KBL-S (G) 		0 0x6 0x9 0xE Family 6 Model 158
• KBL-Y • KBL-U (R) 0 0x6 0x8 0xE Family 6 Model 142
Amber Lake • AML-Y (Stepping 9) 0 0x6 0x8 0xE Family 6 Model 142
Whiskey Lake • WHL-U (Stepping 11/12)
Skylake (Client) • SKL-H • SKL-S • SKL-DT 0 0x6 0x5 0xE Family 6 Model 94
• SKL-Y • SKL-U 0 0x6 0x4 0xE Family 6 Model 78
Broadwell (Client) • BDW-H • BDW-C • BDW-W 0 0x6 0x4 0x7 Family 6 Model 71
• BDW-Y • BDW-U • BDW-S 0 0x6 0x3 0xD Family 6 Model 61
Haswell (Client) • HSW-MB (GT3E) 0 0x6 0x4 0x6 Family 6 Model 70
• HSW-U (ULT/ULX/Y) 0 0x6 0x4 0x5 Family 6 Model 69
• HSW-S (H/DT) 0 0x6 0x3 0xC Family 6 Model 60
Ivy Bridge (Client) • IVB-M • IVB-H (Gladden) 0 0x6 0x3 0xA Family 6 Model 58
Sandy Bridge (Client) • SNB-M • SNB-H (Celeron) 0 0x6 0x2 0xA Family 6 Model 42
Westmere (Client) Arrandale, Clarkdale 0 0x6 0x2 0x5 Family 6 Model 37
Nehalem (Client) Auburndale, Havendale 0 0x6 0x1 0xF Family 6 Model 31
Clarksfield 0 0x6 0x1 0xE Family 6 Model 30
Penryn (Client) Penryn, Wolfdale, Yorkfield 0 0x6 0x1 0x7 Family 6 Model 23
Core (Client) Merom L 0 0x6 0x1 0x6 Family 6 Model 22
Merom 0 0x6 0x0 0xF Family 6 Model 15
Modified Pentium M Yonah 0 0x6 0x0 0xE Family 6 Model 14
Pentium M Tolapai 0 0x6 0x1 0x5 Family 6 Model 21
Dothan 0 0x6 0x0 0xD Family 6 Model 13
Banias 0 0x6 0x0 0x9 Family 6 Model 9
P6 (Pentium) Tualatin (Pentium III) 0 0x6 0x0 0xB Family 6 Model 11
Coppermine, Coppermine T 0 0x6 0x0 0x8 Family 6 Model 8
Katmai 0 0x6 0x0 0x7 Family 6 Model 7
0 0x6 0x0 0x6 Family 6 Model 6
Deschutes (Pentium III) 0 0x6 0x0 0x5 Family 6 Model 5
Klamath (Pentium II) 0 0x6 0x0 0x3 Family 6 Model 3
Pentium Pro 0 0x6 0x0 0x1 Family 6 Model 1

Family 5[edit]

Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
Lakemont
(Lake) 		Quark D1000 0 0x5 0x0 0xA Family 5 Model 10
Quark X1000 0 0x5 0x0 0x9 Family 5 Model 9
P5 (1993)
• Pentium 		P55C (Mobile) 0 0x5 0x0 0x8 Family 5 Model 8
0 0x5 0x0 0x7 Family 5 Model 7
P55C (Pentium MMX) 0 0x5 0x0 0x4 Family 5 Model 4
P54CS (Pentium 75) 0 0x5 0x0 0x2 Family 5 Model 2
P54, P54CQS 0 0x5 0x0 0x1 Family 5 Model 1
P5 (A-step) 0 0x5 0x0 0x0 Family 5 Model 0

Family 4[edit]

Microarchitecture Core Extended
Family 		Family Extended
Model 		Model Family • Model
Intel 486
(80486) 		Intel 80486 0 0x4 0x0 0x9 Family 4 Model 9
Intel 486DX4 0 0x4 0x0 0x8 Family 4 Model 8
Intel 80486 0 0x4 0x0 0x7 Family 4 Model 7
Intel 80486 0 0x4 0x0 0x5 Family 4 Model 5
Intel 486SL 0 0x4 0x0 0x4 Family 4 Model 4
Intel 486DX2 0 0x4 0x0 0x3 Family 4 Model 3
Intel 486SX 0 0x4 0x0 0x2 Family 4 Model 2
Intel 486DX 0 0x4 0x0 0x1 Family 4 Model 1

Family 3[edit]

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