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{{armh title|Cortex-A53|arch}}
 
{{armh title|Cortex-A53|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
| name         = Cortex-A53
+
|atype=CPU
−
| designer     = ARM Holdings
+
|name=Cortex-A53
−
| manufacturer =  
+
|designer=ARM Holdings
−
| introduction = July 2014
+
|manufacturer=TSMC
−
| phase-out    =
+
|manufacturer 2=Samsung
−
| process       = 28 nm
+
|manufacturer 3=GlobalFoundries
−
| process 2    = 20 nm
+
|Max clock rate=2,45GHz boost
−
| process 3    = 16 nm
+
|introduction=October 30, 2012
−
| process 4    = 14 nm
+
|process=40 nm
−
| process 5    = 10 nm
+
|process 2=28 nm
−
| cores         = 1
+
|process 3=20 nm
−
| cores 2       = 2
+
|process 4=16 nm
−
| cores 3       = 3
+
|process 5=14 nm
−
| cores 4       = 4
+
|process 6=10 nm
 +
|cores=1
 +
|cores 2=2
 +
|cores 3=3
 +
|cores 4=4
 +
|type=In-order
 +
|oooe=No
 +
|speculative=Yes
 +
|renaming=No
 +
|stages=8
 +
|decode=2-way
 +
|isa=ARMv8
 +
|feature=Hardware virtualization
 +
|extension=FPU
 +
|extension 2=NEON
 +
|extension 3=TrustZone
 +
|l1i=8-64 KiB
 +
|l1i per=core
 +
|l1i desc=2-way set associative
 +
|l1d=8-64 KiB
 +
|l1d per=core
 +
|l1d desc=4-way set associative
 +
|l2=128 KiB - 2 MiB
 +
|l2 per=cluster
 +
|l2 desc=16-way set associative
 +
|predecessor=Cortex-A7
 +
|predecessor link=arm_holdings/microarchitectures/cortex-a7
 +
|successor=Cortex-A55
 +
|successor link=arm_holdings/microarchitectures/cortex-a55
 +
|pipeline=Yes
 +
|issues=2
 +
|core names=<!-- Yes if specify -->
 +
}}
 +
'''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
  
−
| pipeline      = Yes
+
Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
−
| type          =
 
−
| type 2        =
 
−
| type N        =
 
−
| OoOE          = No
 
−
| speculative  = No
 
−
| renaming      =
 
−
| isa          = ARMv8
 
−
| stages        = 8
 
−
| stages min    =
 
−
| stages max    =
 
−
| issues        = 2
 
  
−
| inst          = Yes
+
== Process Technology ==
−
| feature      = Hardware virtualization
+
{{empty section}}
−
| extension    = NEON
 
−
| extension 2  = TrustZone
 
−
| extension N  =
 
  
−
| cache        = Yes
+
== Compiler support ==
−
| l1i          = 8-64 KiB
+
{| class="wikitable"
−
| l1i per      = core
+
|-
−
| l1i desc      = 2-way set associative
+
! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target
−
| l1d          = 8-64 KiB
+
|-
−
| l1d per      = core
+
| [[GCC]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
−
| l1d desc      = 4-way set associative
+
|-
−
| l2            = 128 KiB - 2 MiB
+
| [[LLVM]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
−
| l2 per        = cluster
+
|}
−
| l2 desc      = 16-way set associative
 
−
| l3            =
 
−
| l3 per        =  
 
−
| l3 desc      =
 
  
−
| core names      = <!-- Yes if specify -->
+
Note that for big.LITTLE systems it's possible to specify more specific performance tunes:
−
| core name        =
 
−
| core name 2      =
 
−
| core name N      =
 
  
−
| succession      = Yes
+
* <code>-mtune=cortex-a57.cortex-a53</code>
−
| predecessor      = Cortex-A9
+
* <code>-mtune=cortex-a72.cortex-a53</code>
−
| predecessor link = arm_holdings/microarchitectures/cortex-a9
+
* <code>-mtune=cortex-a73.cortex-a53</code>
−
| successor        =  
 
−
| successor link  =
 
−
| successor 2      =
 
−
| successor 2 link =
 
−
}}
 
−
'''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A9|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 
  
−
Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
  
−
== Process Technology ==
 
−
{{empty section}}
 
  
 
== Architecture ==
 
== Architecture ==
 +
=== Key changes from {{\\|Cortex-A7}} ===
 +
{{empty section}}
 +
=== Block Diagram ===
 +
{{empty section}}
 +
=== Memory Hierarchy ===
 
{{empty section}}
 
{{empty section}}
 +
 +
== Licensees ==
 +
Arm named the following companies as licensees.
 +
 +
{{collist
 +
|count = 2
 +
|
 +
* [[Allwinner]] (A64, H5, H6, H64)
 +
* [[Amlogic]] (S805X, S905, S912)
 +
* [[AMD]]
 +
* [[Broadcom]]
 +
* [[Samsung]]
 +
* [[Altera]]
 +
* [[STMicroelectronics]]
 +
* [[MediaTek]]
 +
* [[Qualcomm]]
 +
* [[Xilinx]]
 +
}}
  
 
== Die ==
 
== Die ==
−
{{empty section}}
+
=== 20 nm ===
 +
==== Samsung [[Exynos 5433]] ====
 +
* Samsung [[20 nm process]]
 +
* 113 mm² die size
 +
* Mali-T760 (6 EU)
 +
* Quad-core Cortex-A53 ([[small cores]])
 +
** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
 +
** 4.4 mm² per cluster
 +
*** ~1 mm² per core
 +
*** ~0.55 mm² for 256 KiB L2 cache
 +
* Quad-core {{\\|Cortex-A57}} ([[big cores]])
 +
** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
 +
** 15.85 mm² per cluster
 +
*** ~3 mm² per core
 +
*** ~3.87 mm² for 2 MiB L2 cache
 +
 
 +
 
 +
:[[File:exynos 5433 die.png|600px]]
 +
 
 +
==== MediaTek [[Helio X20]] ====
 +
 
 +
* TSMC [[20 nm process]]
 +
* 100 mm² die size
 +
* Quad-core ULP Cortex-A53
 +
** ~21.81 mm² per cluster
 +
*** ~4.23 mm² per core
 +
* Quad-core efficient Cortex-A53
 +
** ~29.73 mm² per cluster
 +
*** ~5.41 mm² per core
 +
* Dual-core High-performance {{\\|Cortex-A72}} +  1 MiB L2
 +
** ~27.36 mm² per cluster
 +
*** ~ 9.60 mm² per core
 +
*** ~ 7.50 mm² for 1 MiB L2
 +
 
 +
 
 +
:[[File:mt6797 die.png|600px]]
 +
 
 +
=== 16 nm ===
 +
==== Renesas [[R-Car H3]] ====
 +
* TSMC [[16 nm process]]
 +
* 12.94 mm × 8.61 mm
 +
* 111.36 mm² die size
 +
* Quad-core Cortex-A53
 +
** ~3.27 mm² cluster
 +
** ~0.60 mm² core
 +
** ~0.7`mm² L2 cache
 +
* Quad-core {{\\|Cortex-A57}}
 +
** ~10.21 mm² cluster
 +
** ~1.66 mm² core
 +
** ~3.28 mm² L2 cache
 +
* {{\\|Cortex-R7}} (dual-core [[lock-step]])
 +
** ~1.04 mm² cluster
 +
* GX6650 GPU
 +
** ~28.12 mm²
 +
 
 +
 
 +
: [[File:r-car h3 die shot.png|650px]]
  
 
== All Cortex-A53 Chips ==
 
== All Cortex-A53 Chips ==
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           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
-->
−
<table class="wikitable sortable">
+
{{comp table start}}
−
<tr><th colspan="10" style="background:#D6D6FF;">Cortex-A53 Chips</th></tr>
+
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
−
<tr><th colspan="8">Main processor</th><th colspan="2">IGP</th></tr>
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">List of all Cortex-A53 Chips</th></tr>
−
<tr><th>Model</th><th>Designer</th><th>Family</th><th>Core</th><th>Launched</th><th>Cores</th><th>Frequency</th><th>Max Mem</th><th>Name</th><th>Freq</th></tr>
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
 +
{{comp table header 1|cols=Launched, Designer, Family, Process, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}}
 
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]
 
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 +
|?first launched
 
  |?designer
 
  |?designer
 
  |?microprocessor family
 
  |?microprocessor family
 +
|?process
 
  |?core name
 
  |?core name
−
|?first launched
 
 
  |?core count
 
  |?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 
  |?base frequency#GHz
 
  |?base frequency#GHz
 
  |?max memory#GiB
 
  |?max memory#GiB
 +
|?integrated gpu designer
 
  |?integrated gpu
 
  |?integrated gpu
 
  |?integrated gpu base frequency
 
  |?integrated gpu base frequency
−
|?has simultaneous multithreading
 
 
  |format=template
 
  |format=template
−
  |template=proc table 2
+
  |template=proc table 3
 
  |searchlabel=
 
  |searchlabel=
−
  |userparam=11
+
|sort=microprocessor family, model number
 +
|order=asc,asc
 +
  |userparam=15
 
  |mainlabel=-
 
  |mainlabel=-
 +
|limit=100
 +
|valuesep=,
 
}}
 
}}
−
{{table count|col=11|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]}}
+
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]}}
 
</table>
 
</table>
 +
{{comp table end}}
 +
 +
== Bibliography ==
 +
* Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
 +
* Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.

Latest revision as of 12:01, 6 March 2022

Edit Values
Cortex-A53 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC, Samsung, GlobalFoundries
IntroductionOctober 30, 2012
Process40 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm
Core Configs1, 2, 3, 4
Pipeline
TypeIn-order
OoOENo
SpeculativeYes
Reg RenamingNo
Stages8
Decode2-way
Instructions
ISAARMv8
ExtensionsFPU, NEON, TrustZone
Cache
L1I Cache8-64 KiB/core
2-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache128 KiB - 2 MiB/cluster
16-way set associative
Succession

Cortex-A53 (formerly Apollo) is an ultra-high efficiency microarchitecture designed by ARM Holdings as a successor to the Cortex-A7. The Cortex-A53, which implemented the ARMv8 ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on Cortex-A57 or Cortex-A72) in big.LITTLE configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

Process Technology[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable Arch-Target
GCC -march=armv8-a -mtune=cortex-a53 -mcpu=cortex-a53
LLVM -march=armv8-a -mtune=cortex-a53 -mcpu=cortex-a53

Note that for big.LITTLE systems it's possible to specify more specific performance tunes:

  • -mtune=cortex-a57.cortex-a53
  • -mtune=cortex-a72.cortex-a53
  • -mtune=cortex-a73.cortex-a53


Architecture[edit]

Key changes from Cortex-A7[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Licensees[edit]

Arm named the following companies as licensees.

Die[edit]

20 nm[edit]

Samsung Exynos 5433[edit]

  • Samsung 20 nm process
  • 113 mm² die size
  • Mali-T760 (6 EU)
  • Quad-core Cortex-A53 (small cores)
    • 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
    • 4.4 mm² per cluster
      • ~1 mm² per core
      • ~0.55 mm² for 256 KiB L2 cache
  • Quad-core Cortex-A57 (big cores)
    • 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
    • 15.85 mm² per cluster
      • ~3 mm² per core
      • ~3.87 mm² for 2 MiB L2 cache


exynos 5433 die.png

MediaTek Helio X20[edit]

  • TSMC 20 nm process
  • 100 mm² die size
  • Quad-core ULP Cortex-A53
    • ~21.81 mm² per cluster
      • ~4.23 mm² per core
  • Quad-core efficient Cortex-A53
    • ~29.73 mm² per cluster
      • ~5.41 mm² per core
  • Dual-core High-performance Cortex-A72 + 1 MiB L2
    • ~27.36 mm² per cluster
      • ~ 9.60 mm² per core
      • ~ 7.50 mm² for 1 MiB L2


mt6797 die.png

16 nm[edit]

Renesas R-Car H3[edit]

  • TSMC 16 nm process
  • 12.94 mm × 8.61 mm
  • 111.36 mm² die size
  • Quad-core Cortex-A53
    • ~3.27 mm² cluster
    • ~0.60 mm² core
    • ~0.7`mm² L2 cache
  • Quad-core Cortex-A57
    • ~10.21 mm² cluster
    • ~1.66 mm² core
    • ~3.28 mm² L2 cache
  • Cortex-R7 (dual-core lock-step)
    • ~1.04 mm² cluster
  • GX6650 GPU
    • ~28.12 mm²


r-car h3 die shot.png

All Cortex-A53 Chips[edit]

 List of all Cortex-A53 Chips
 Main processorIGP
ModelLaunchedDesignerFamilyProcessCoreCTL2$L3$FrequencyMax MemDesignerNameFrequency
7270November 2016Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A53221 GHz
1,000 MHz
1,000,000 kHz
7420April 2015Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A53, Cortex-A57882.1 GHz
2,100 MHz
2,100,000 kHz
, 1.5 GHz
1,500 MHz
1,500,000 kHz
757030 August 2016Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A53441.4 GHz
1,400 MHz
1,400,000 kHz
7580June 2015Samsung, ARM HoldingsExynos28 nm
0.028 μm
2.8e-5 mm
Cortex-A53881.6 GHz
1,600 MHz
1,600,000 kHz
787017 February 2016Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A53881.6 GHz
1,600 MHz
1,600,000 kHz
787217 January 2018Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
662 GHz
2,000 MHz
2,000,000 kHz
, 1.5 GHz
1,500 MHz
1,500,000 kHz
7880March 2017Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A53881.9 GHz
1,900 MHz
1,900,000 kHz
788513 February 2018Samsung, ARM HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A73, Cortex-A53882.2 GHz
2,200 MHz
2,200,000 kHz
, 1.6 GHz
1,600 MHz
1,600,000 kHz
790421 January 2019Samsung, Arm HoldingsExynos14 nm
0.014 μm
1.4e-5 mm
Cortex-A73, Cortex-A53881.8 GHz
1,800 MHz
1,800,000 kHz
889021 February 2016SamsungExynos14 nm
0.014 μm
1.4e-5 mm
Exynos M1, Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
, 0.25 MiB
256 KiB
262,144 B
2.441406e-4 GiB
2.3 GHz
2,300 MHz
2,300,000 kHz
, 1.6 GHz
1,600 MHz
1,600,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
ARM HoldingsMali-T880
889529 March 2017Samsung, ARM HoldingsExynos10 nm
0.01 μm
1.0e-5 mm
Cortex-A53, Mongoose 2881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2.314 GHz
2,314 MHz
2,314,000 kHz
, 1.69 GHz
1,690 MHz
1,690,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
ARM HoldingsMali-G71
91109 August 2018Samsung, ARM HoldingsExynos10 nm
0.01 μm
1.0e-5 mm
Cortex-A53221 GiB
1,024 MiB
1,048,576 KiB
1,073,741,824 B
9.765625e-4 TiB
ARM HoldingsMali-T720
9610October 2018Samsung, ARM HoldingsExynos10 nm
0.01 μm
1.0e-5 mm
Cortex-A73, Cortex-A53882.3 GHz
2,300 MHz
2,300,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
ARM HoldingsMali-G72
Helio A2217 July 2018MediaTek, ARM HoldingsHelio12 nm
0.012 μm
1.2e-5 mm
Cortex-A53442 GHz
2,000 MHz
2,000,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
Imagination TechnologiesPowerVR GE8320
Helio X1027 March 2015MediaTek, ARM HoldingsHelio28 nm
0.028 μm
2.8e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2 GHz
2,000 MHz
2,000,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
Imagination TechnologiesPowerVR G6200
Helio X10 M27 March 2015MediaTek, ARM HoldingsHelio28 nm
0.028 μm
2.8e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2 GHz
2,000 MHz
2,000,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
Imagination TechnologiesPowerVR G6200
Helio X10 T27 March 2015MediaTek, ARM HoldingsHelio28 nm
0.028 μm
2.8e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2.2 GHz
2,200 MHz
2,200,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
Imagination TechnologiesPowerVR G6200
Helio X2016 March 2016MediaTek, ARM HoldingsHelio20 nm
0.02 μm
2.0e-5 mm
Cortex-A53, Cortex-A7210101.85 GHz
1,850 MHz
1,850,000 kHz
, 1.4 GHz
1,400 MHz
1,400,000 kHz
, 2.1 GHz
2,100 MHz
2,100,000 kHz
ARM HoldingsMali-T880
Helio X20 M16 March 2016MediaTek, ARM HoldingsHelio20 nm
0.02 μm
2.0e-5 mm
Cortex-A53, Cortex-A7210102 GHz
2,000 MHz
2,000,000 kHz
, 1.85 GHz
1,850 MHz
1,850,000 kHz
, 1.4 GHz
1,400 MHz
1,400,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-T880
Helio X232 December 2016MediaTek, ARM HoldingsHelio20 nm
0.02 μm
2.0e-5 mm
Cortex-A53, Cortex-A7210102.3 GHz
2,300 MHz
2,300,000 kHz
, 1.85 GHz
1,850 MHz
1,850,000 kHz
, 1.4 GHz
1,400 MHz
1,400,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
ARM HoldingsMali-T880
Helio X2516 March 2016ARM Holdings, MediaTekHelio20 nm
0.02 μm
2.0e-5 mm
Cortex-A53, Cortex-A7210102.5 GHz
2,500 MHz
2,500,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
, 1.55 GHz
1,550 MHz
1,550,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-T880
Helio X272 December 2016MediaTek, ARM HoldingsHelio20 nm
0.02 μm
2.0e-5 mm
Cortex-A53, Cortex-A7210102.6 GHz
2,600 MHz
2,600,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
, 1.6 GHz
1,600 MHz
1,600,000 kHz
ARM HoldingsMali-T880
Helio X3027 February 2017MediaTek, ARM HoldingsHelio10 nm
0.01 μm
1.0e-5 mm
Cortex-A35, Cortex-A53, Cortex-A7310102.5 GHz
2,500 MHz
2,500,000 kHz
, 2.2 GHz
2,200 MHz
2,200,000 kHz
, 1.9 GHz
1,900 MHz
1,900,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
Imagination TechnologiesPowerVR GT7400 Plus
P10January 2016MediaTek, ARM HoldingsHelio28 nm
0.028 μm
2.8e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2 GHz
2,000 MHz
2,000,000 kHz
, 1.2 GHz
1,200 MHz
1,200,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
ARM HoldingsMali-T860
P10 MJanuary 2016MediaTek, ARM HoldingsHelio28 nm
0.028 μm
2.8e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
, 1.2 GHz
1,200 MHz
1,200,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
ARM HoldingsMali-T860
P15April 2017MediaTek, ARM HoldingsHelio28 nm
0.028 μm
2.8e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2.2 GHz
2,200 MHz
2,200,000 kHz
, 1.2 GHz
1,200 MHz
1,200,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
ARM HoldingsMali-T860
P20November 2016MediaTek, ARM HoldingsHelio16 nm
0.016 μm
1.6e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2.3 GHz
2,300 MHz
2,300,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-T880
P2222 May 2018MediaTek, ARM HoldingsHelio12 nm
0.012 μm
1.2e-5 mm
Cortex-A53882 GHz
2,000 MHz
2,000,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
Imagination TechnologiesPowerVR GE8320
P2328 August 2017MediaTek, ARM HoldingsHelio16 nm
0.016 μm
1.6e-5 mm
Cortex-A53881.65 GHz
1,650 MHz
1,650,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-G71
P258 February 2017MediaTek, ARM HoldingsHelio16 nm
0.016 μm
1.6e-5 mm
Cortex-A53882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2.6 GHz
2,600 MHz
2,600,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-T880
P3028 August 2017MediaTek, ARM HoldingsHelio16 nm
0.016 μm
1.6e-5 mm
Cortex-A53881.65 GHz
1,650 MHz
1,650,000 kHz
, 2.3 GHz
2,300 MHz
2,300,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-G71
P6026 February 2018ARM Holdings, MediaTekHelio12 nm
0.012 μm
1.2e-5 mm
Cortex-A53, Cortex-A73882 GHz
2,000 MHz
2,000,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
ARM HoldingsMali-G72
P7024 October 2018MediaTek, ARM HoldingsHelio12 nm
0.012 μm
1.2e-5 mm
Cortex-A73, Cortex-A53882.1 GHz
2,100 MHz
2,100,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
ARM HoldingsMali-G72
71019 July 2018HiSilicon, ARM HoldingsKirin12 nm
0.012 μm
1.2e-5 mm
Cortex-A53, Cortex-A73882.2 GHz
2,200 MHz
2,200,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
6 GiB
6,144 MiB
6,291,456 KiB
6,442,450,944 B
0.00586 TiB
ARM HoldingsMali-G51
9701 September 2017HiSilicon, ARM HoldingsKirin10 nm
0.01 μm
1.0e-5 mm
Cortex-A53, Cortex-A73881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
, 2.36 GHz
2,360 MHz
2,360,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
ARM HoldingsMali-G72
H3March 2018Renesas, ARM HoldingsR-Car16 nm
0.016 μm
1.6e-5 mm
Cortex-A53, Cortex-A57, Cortex-R7992 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
Imagination TechnologiesPowerVR GX6650
H3 (SiP)March 2018Renesas, ARM HoldingsR-Car16 nm
0.016 μm
1.6e-5 mm
Cortex-A53, Cortex-A57, Cortex-R7992.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
Imagination TechnologiesPowerVR GX6650
M3October 2016Renesas, ARM HoldingsR-Car16 nm
0.016 μm
1.6e-5 mm
Cortex-A53, Cortex-A57, Cortex-R7771.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
Imagination TechnologiesPowerVR GX6250
M3 (SiP)October 2016ARM Holdings, RenesasR-Car16 nm
0.016 μm
1.6e-5 mm
Cortex-A53, Cortex-A57, Cortex-R7771.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
Imagination TechnologiesPowerVR GX6250
SDM42926 June 2018Qualcomm, ARM HoldingsSnapdragon 40012 nm
0.012 μm
1.2e-5 mm
Cortex-A53441.95 GHz
1,950 MHz
1,950,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
QualcommAdreno 504
SDM43926 June 2018QualcommSnapdragon 40012 nm
0.012 μm
1.2e-5 mm
Cortex-A53881.45 GHz
1,450 MHz
1,450,000 kHz
, 1.95 GHz
1,950 MHz
1,950,000 kHz
4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
QualcommAdreno 505
Snapdragon 46020 January 2020QualcommSnapdragon 40011 nm
0.011 μm
1.1e-5 mm
Kryo 240 Gold, Kryo 240 Silver881.8 GHz
1,800 MHz
1,800,000 kHz
QualcommAdreno 610
SDM63226 June 2018QualcommSnapdragon 60014 nm
0.014 μm
1.4e-5 mm
Kryo 250 Silver, Kryo 250 Gold881.8 GHz
1,800 MHz
1,800,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 506
SDM6608 May 2017Qualcomm, ARM HoldingsSnapdragon 60014 nm
0.014 μm
1.4e-5 mm
Kryo 260 Gold, Kryo 260 Silver882.2 GHz
2,200 MHz
2,200,000 kHz
, 1.84 GHz
1,840 MHz
1,840,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 512
SM61259 April 2019Qualcomm, ARM HoldingsSnapdragon 60011 nm
0.011 μm
1.1e-5 mm
Kryo 260 Gold, Kryo 260 Silver881.8 GHz
1,800 MHz
1,800,000 kHz
, 4.5 GHz
4,500 MHz
4,500,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 610
Snapdragon 66220 January 2020QualcommSnapdragon 60011 nm
0.011 μm
1.1e-5 mm
Kryo 260 Gold, Kryo 260 Silver881.8 GHz
1,800 MHz
1,800,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 610
BM188017 October 2018BitmainSophonCortex-A53, RISC-V4 GiB
4,096 MiB
4,194,304 KiB
4,294,967,296 B
0.00391 TiB
S1Xiaomi, ARM HoldingsSurge28 nm
0.028 μm
2.8e-5 mm
Cortex-A53881.4 GHz
1,400 MHz
1,400,000 kHz
, 2.2 GHz
2,200 MHz
2,200,000 kHz
ARM HoldingsMali-T860
S2Xiaomi, ARM HoldingsSurge10 nm
0.01 μm
1.0e-5 mm
Cortex-A53, Cortex-A7388ARM HoldingsMali-G71
Count: 50

Bibliography[edit]

  • Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
  • Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a53&oldid=99793"
Facts about "Cortex-A53 - Microarchitectures - ARM"
RDF feed
codenameCortex-A53 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedOctober 30, 2012 +
full page namearm holdings/microarchitectures/cortex-a53 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +, Samsung + and GlobalFoundries +
microarchitecture typeCPU +
nameCortex-A53 +
pipeline stages8 +
process40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +