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+ | == Many-core == | ||
+ | {{work-in-progress}} | ||
+ | |||
+ | === Initial effort & Polaris === | ||
+ | Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum. | ||
+ | |||
+ | The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherit problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance. | ||
+ | |||
+ | === Larrabee === | ||
+ | {{empty section}} |
Revision as of 09:50, 11 April 2018
Below is a list of Intel microarchitectures:
Contents
CPU Microarchitectures
... further resultsIntel CPU Microarchitectures | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
General | Details | ||||||||||
µarch | Introduction | Phase-out | Process | Cores | Pipeline | ||||||
80386 | March 1984 | 1989 | 1,500 nm 1.5 μm 0.0015 mm | ||||||||
80486 | 10 April 1989 | 1995 | 1,000 nm 1 μm , 800 nm0.001 mm 0.8 μm , 600 nm8.0e-4 mm 0.6 μm 6.0e-4 mm | ||||||||
P5 | April 1993 | October 1995 | 600 nm 0.6 μm 6.0e-4 mm | ||||||||
P6 | October 1995 | December 2000 | 350 nm 0.35 μm , 250 nm3.5e-4 mm 0.25 μm 2.5e-4 mm | ||||||||
NetBurst | 20 November 2000 | April 2006 | 180 nm 0.18 μm 1.8e-4 mm | ||||||||
Merced | June 2001 | 180 nm 0.18 μm 1.8e-4 mm | 1 | ||||||||
McKinley | 8 July 2002 | 180 nm 0.18 μm 1.8e-4 mm | 1, 2 | ||||||||
Pentium M | 2003 | 2005 | 130 nm 0.13 μm , 90 nm1.3e-4 mm 0.09 μm 9.0e-5 mm | ||||||||
Madison | 30 June 2003 | 130 nm 0.13 μm 1.3e-4 mm | 1 | ||||||||
Madison 9M | 8 November 2004 | 130 nm 0.13 μm 1.3e-4 mm | 1 | ||||||||
Modified Pentium M | 2006 | 2008 | 65 nm 0.065 μm 6.5e-5 mm | ||||||||
Core | April 2006 | May 2009 | 65 nm 0.065 μm 6.5e-5 mm | ||||||||
Montecito | 18 July 2006 | 90 nm 0.09 μm 9.0e-5 mm | 1, 2 | ||||||||
Polaris | February 2007 | 65 nm 0.065 μm 6.5e-5 mm | 80 | 9 | |||||||
Montvale | 31 October 2007 | 90 nm 0.09 μm 9.0e-5 mm | 1, 2 | ||||||||
Penryn | November 2007 | September 2008 | 45 nm 0.045 μm 4.5e-5 mm | ||||||||
Bonnell | 2 March 2008 | 2011 | 45 nm 0.045 μm 4.5e-5 mm | 1, 2 | 16 | 19 | |||||
Nehalem | August 2008 | March 2010 | 45 nm 0.045 μm 4.5e-5 mm | ||||||||
Rock Creek | December 2009 | 45 nm 0.045 μm 4.5e-5 mm | 48 | ||||||||
Westmere | January 2010 | August 2011 | 32 nm 0.032 μm 3.2e-5 mm | ||||||||
Tukwila | 8 February 2010 | 65 nm 0.065 μm 6.5e-5 mm | 1, 2 | ||||||||
Knights Ferry | 31 May 2010 | 2011 | 45 nm 0.045 μm 4.5e-5 mm | 32 | |||||||
Sandy Bridge (client) | 13 September 2010 | November 2012 | 32 nm 0.032 μm 3.2e-5 mm | 2, 4 | 14 | 19 | |||||
Saltwell | 2011 | 2013 | 32 nm 0.032 μm 3.2e-5 mm | 1, 2 | 16 | ||||||
Knights Corner | 2011 | 2013 | 22 nm 0.022 μm 2.2e-5 mm | 57, 60, 61 | |||||||
Ivy Bridge | 4 May 2011 | April 2013 | 22 nm 0.022 μm 2.2e-5 mm | ||||||||
Poulson | 8 November 2012 | 32 nm 0.032 μm 3.2e-5 mm | 1, 2 | ||||||||
Silvermont | 2013 | 2015 | 22 nm 0.022 μm 2.2e-5 mm | 1, 2, 4, 8 | 12 | 14 | |||||
Haswell | 4 June 2013 | 2015 | 22 nm 0.022 μm 2.2e-5 mm | 2, 4, 6, 8, 16, 10, 12, 14, 18 | 14 | 19 | |||||
Broadwell | October 2014 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22 | 14 | 19 | ||||||
Airmont | 2015 | 2017 | 14 nm 0.014 μm 1.4e-5 mm | 1, 2, 4, 8 | 12 | 14 | |||||
Skylake (client) | 5 August 2015 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4 | 14 | 19 | ||||||
Kaby Lake | 30 August 2016 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4 | 14 | 19 | ||||||
Goldmont | 30 August 2016 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4, 8, 12, 16 | 12 | 14 | ||||||
Kittson | 2017 | 22 nm 0.022 μm 2.2e-5 mm | 1, 2 | ||||||||
Skylake (server) | 4 May 2017 | 14 nm 0.014 μm 1.4e-5 mm | 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28 | 14 | 19 | ||||||
Coffee Lake | 5 October 2017 | 14 nm 0.014 μm 1.4e-5 mm | 14 | 19 | |||||||
Goldmont Plus | 11 December 2017 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4 | ||||||||
Knights Mill | 18 December 2017 | 9 August 2019 | 14 nm 0.014 μm 1.4e-5 mm | ||||||||
Palm Cove | 2018 | 10 nm 0.01 μm 1.0e-5 mm | 2 | 14 | 19 | ||||||
Whiskey Lake | April 2018 | 4 | 14 | 19 | |||||||
Amber Lake | April 2018 | 14 nm 0.014 μm 1.4e-5 mm | 2 | 14 | 19 | ||||||
Cannon Lake | 15 May 2018 | 10 nm 0.01 μm 1.0e-5 mm | 2 | 14 | 19 | ||||||
Tremont | 2019 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Snow Ridge | 2019 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Sunny Cove | 2019 | 2021 | 10 nm 0.01 μm 1.0e-5 mm | 2, 4, 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 40 | 14 | 19 | |||||
Lakefield | 2019 | 22 nm 0.022 μm , 10 nm2.2e-5 mm 0.01 μm 1.0e-5 mm | 5 | ||||||||
Cascade Lake | 2019 | 14 nm 0.014 μm 1.4e-5 mm | 2, 4, 6, 8, 10, 12, 16, 18, 20, 22, 24, 26, 28, 32, 48, 56 | 14 | 19 | ||||||
Ice Lake (client) | 27 May 2019 | 10 nm 0.01 μm 1.0e-5 mm | 2, 4 | 14 | 19 | ||||||
Willow Cove | 2020 | 10 nm 0.01 μm 1.0e-5 mm | 2, 4, 6, 8 | 14 | 19 |
GPU Microarchitectures
Intel GPU Microarchitectures | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
General | Details | ||||||||||
µarch | Introduction | Phase-out | Process | ||||||||
Gen1 | 1998 | ||||||||||
Gen2 | 2002 | ||||||||||
Gen3 | 2004 | ||||||||||
Gen3.5 | 2005 | 90 nm 0.09 μm 9.0e-5 mm | |||||||||
Gen4 | 2006 | 65 nm 0.065 μm 6.5e-5 mm | |||||||||
Gen5 | 3 June 2008 | 45 nm 0.045 μm 4.5e-5 mm | |||||||||
Larrabee | 12 August 2008 | 2010 | 32 nm 0.032 μm , 45 nm3.2e-5 mm 0.045 μm 4.5e-5 mm | ||||||||
Gen5.75 | January 2010 | 45 nm 0.045 μm 4.5e-5 mm | |||||||||
Gen6 | 13 September 2010 | 32 nm 0.032 μm 3.2e-5 mm | |||||||||
Gen7 | 4 May 2011 | 22 nm 0.022 μm 2.2e-5 mm | |||||||||
Gen7.5 | 4 June 2013 | 22 nm 0.022 μm 2.2e-5 mm | |||||||||
Gen8 | October 2014 | 14 nm 0.014 μm 1.4e-5 mm | |||||||||
Gen9 | 5 August 2015 | 14 nm 0.014 μm 1.4e-5 mm | |||||||||
Gen9.5 | 30 August 2016 | 14 nm 0.014 μm 1.4e-5 mm | |||||||||
Gen11 | 2018 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Gen10 | 2018 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Arctic Sound | 2020 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Gen12 | 2020 | 10 nm 0.01 μm 1.0e-5 mm | |||||||||
Jupiter Sound | 2022 | 10 nm 0.01 μm 1.0e-5 mm |
Many-core
Initial effort & Polaris
Intel actual large effort research into the area of many-core started after the February 2004 Intel Developer Forum following Pradeep Dubey famous keynote titled "The Era of Tera." Around the 2004-2005 Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the Tera-scale Computing Research Program which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
The first product to come directly from that project was Polaris, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a mesh topology. Fabricated on a 65 nm process, the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherit problems dealing with a large amount of cores such as the bandwidth. 3D stacked SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 teraFLOPS of sustained performance.
Larrabee
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