• mosfet
  ...o cheaper and have relatively simple processing steps, resulting in high [[manufacturing yield]]. ...ngle crystals of silicon. Each transistor consists of a body - the silicon wafer. The body is often grounded, often considered the [[reference node]]. Each
  193 KB (26,874 words) - 17:01, 6 September 2024
• mask
  ...rough the mask, the detailed device image can then be projected onto the [[wafer]] (see [[photoresist]]). The transmitted image is often passed through some ...o a pattern that could be printed in a single exposure to cover the entire wafer without any optical de-magnification. Today, the terms are often used synon
  3 KB (533 words) - 16:17, 29 January 2024
• 28 nm lithography process
  ...m lithography process|22 nm]] processes. Commercial [[integrated circuit]] manufacturing using 28 nm process began in 2011. This technology superseded by commercial | process 1 wafer type = Bulk
  6 KB (711 words) - 16:01, 26 March 2019
• 32 nm lithography process
  ...ography process|40 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 32 nm process began in 2010. This technology was superseded by the [[ | process 1 wafer type = Bulk
  10 KB (1,090 words) - 18:14, 8 July 2021
• 14 nm lithography process
  The '''14 nanometer (14 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[22 nm proc | process 1 wafer type = Bulk
  17 KB (2,243 words) - 18:32, 25 May 2023
• 45 nm lithography process
  ...ography process|55 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 45 nm process began in 2007. This technology was superseded by the [[ ...is the first time high-k + metal gate transistors was used in high-volume manufacturing process.
  5 KB (602 words) - 04:51, 20 July 2018
• intel/microarchitectures/bonnell
  ! colspan="2" | 45 nm Manufacturing Fabs ...using a [[45 nm process]]. Intel's 45 nm process is the first high-volume manufacturing process to introduce High-k + metal gate transistors.
  38 KB (5,468 words) - 19:29, 23 May 2019
• intel/microarchitectures/broadwell (client)
  ! colspan="2" | 14 nm Manufacturing Fabs ...on-processor-D-1500-wafer.jpg|right|thumb|350px|Broadwell {{intel|Xeon D}} wafer]]
  14 KB (1,891 words) - 13:37, 6 January 2022
• 22 nm lithography process
  ...as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 22 nm process began in 2008 for memory and 2012 for [[MPU]]s. This te | process 1 wafer type = Bulk
  7 KB (891 words) - 08:52, 25 November 2020
• 16 nm lithography process
  ...ography process|20 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial | process 1 wafer type = Bulk
  4 KB (580 words) - 16:00, 26 March 2019
• 20 nm lithography process
  ...as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 20 nm process began in 2014. This technology superseded by commercial | process 1 wafer type = Bulk
  4 KB (483 words) - 22:04, 20 May 2018
• intel/microarchitectures/nehalem (client)
  [[File:Nehalem.jpg|right|thumb|300px|Nehalem wafer]] ! colspan="2" | 45 nm Manufacturing Fabs
  4 KB (459 words) - 20:44, 26 December 2023
• intel/microarchitectures/kaby lake
  ! colspan="2" | 14 nm Manufacturing Fabs ...ain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly [[overclockable]] with models
  38 KB (5,431 words) - 09:41, 8 April 2024
• 40 nm lithography process
  ...m lithography process|32 nm]] processes. Commercial [[integrated circuit]] manufacturing using 40 nm process began in 2008 by leading semiconductor companies such a |Wafer
  2 KB (182 words) - 02:11, 17 August 2023
• 65 nm lithography process
  ...ography process|80 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 65 nm process began in 2005. This technology was superseded by the [[ |Wafer
  4 KB (407 words) - 04:55, 20 July 2018
• 130 nm lithography process
  ...graphy process|150 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 130 nm process began in 2001. This technology was replaced by with [[ |Wafer
  5 KB (500 words) - 15:02, 13 May 2020
• 90 nm lithography process
  ...graphy process|110 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 90 nm process began in 2003. This technology was superseded by the [[ |Wafer
  3 KB (354 words) - 02:09, 17 August 2023
• 180 nm lithography process
  ...graphy process|220 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 180 nm process began in late 1998. This technology was replaced by wi |Wafer
  4 KB (413 words) - 02:04, 17 August 2023
• 10 nm lithography process
  The '''10 nanometer (10 nm) lithography process''' is a [[semiconductor manufacturing]] [[process node]] serving as [[process shrink|shrink]] from the [[14 nm pr ...atterning|patterning]] were introduced for the first time in [[high-volume manufacturing]].
  14 KB (1,903 words) - 05:52, 17 February 2023
• 250 nm lithography process
  ...thography process|350 nm process]] node. Commercial [[integrated circuit]] manufacturing using 250 nm process began in 1997 and was eventually replaced by [[180 nm] ...-use resulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO₂]] dielectric and [[wikipedia:polysilic
  6 KB (661 words) - 15:18, 21 August 2022

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