Skylake (client) - Microarchitectures - Intel

	Edit Values
	Skylake µarch
	General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	August 5, 2015
Process	14 nm
Core Configs	2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28
	Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	14-19
	Instructions
ISA	x86-16, x86-32, x86-64
Extensions	MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
	Cache
L1I Cache	32 KiB/core; 8-way set associative
L1D Cache	32 KiB/core; 8-way set associative
L2 Cache	256 KiB/core; 4-way set associative
L3 Cache	2 MiB/core; Up to 16-way set associative
Side Cache	128 MiB/package; on Iris Pro GPUs only
	Cores
Core Names	Skylake Y,; Skylake U,; Skylake H,; Skylake S,; Skylake DT,; Skylake X,; Skylake SP
	Succession
	Broadwell Kaby Lake

Skylake (SKL) Client Configuration is Intel's successor to Broadwell, a 14 nm process microarchitecture for mainstream workstations, desktops, and mobile devices. Skylake succeeded the short-lived Broadwell which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel.

For desktop and mobile, Skylake is branded as 6th Generation Intel Core i3, Core i5, Core i7 processors. For workstations it's branded as Xeon E3 v5.

1 Codenames
2 Brands
3 Release Dates
4 Process Technology
5 Compatibility
6 Compiler support
- 6.1 CPUID
7 Architecture
- 7.1 Key changes from Broadwell
  - 7.1.1 CPU changes
  - 7.1.2 New instructions
- 7.2 Block Diagram
- 7.3 Memory Hierarchy
8 Overview
- 8.1 Design goals & new goals
- 8.2 SoC design
9 Core
- 9.1 Overview
  - 9.1.1 Configurability
- 9.2 Pipeline
- 9.3 eDRAM architectural changes
10 Server Architecture
- 10.1 Pipeline
- 10.2 Scalability
- 10.3 Integrated Omni-Path
11 New Technologies
- 11.1 Client
  - 11.1.1 Software Guard Extension (SGX)
  - 11.1.2 Memory Protection Extension (MPX)
- 11.2 Server
12 Power
- 12.1 "Speed Shift" (new power management)
  - 12.1.1 SpeedStep Technology Expansion
  - 12.1.2 Power of System (Psys)
- 12.2 Other Power Optimization
  - 12.2.1 AVX2 Power Gating
13 Clock domains
- 13.1 Overclocking
- 13.2 Voltage Control Modes
14 New Integration
- 14.1 Image Processing Unit (IPU)
15 Graphics
- 15.1 Hardware Accelerated Video
16 Sockets/Platform
- 16.1 Packages
17 Die
- 17.1 Client Die
- 17.2 Server Die
18 All Skylake Chips
19 References
20 Documents
21 See also

Codenames

See also: Server Skylake's Codenames

Core	Abbrev	Target
Skylake Y	SKL-Y	2-in-1s detachable, tablets, and computer sticks
Skylake U	SKL-U	Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Skylake H	SKL-H	Ultimate mobile performance, mobile workstations
Skylake S	SKL-S	Desktop performance to value, AiOs, and minis
Skylake DT	SKL-DT	Workstations & entry-level servers

Brands

See also: Server Skylake's Codenames

I ntel released Skylake under 6 main brand families for mainstream workstations, desktops, and mobile.

Logo	Family	General Description	Differentiating Features
Logo	Family	General Description	Cores	HT	AVX	AVX2	TBT	ECC
	Celeron	Entry-level Budget	dual	✘	✘	✘	✘	✘
	Celeron	Entry-level Budget (Embedded)	dual	✘	✘	✘	✘	✔
	Pentium	Budget (Mobile)	dual	✔	✘	✘	✘	✘
	Pentium	Budget (Desktop)	dual	✘	✘	✘	✘	✔
	Core i3	Low-end Performance	dual	✔	✔	✔	✘	✘
	Core i3	Low-end Performance (Desktop/Embedded)	dual	✔	✔	✔	✘	✔
	Core i5	Mid-range Performance	dual	✔	✔	✔	✔	✘
	Core i5	Mid-range Performance	quad	✘	✔	✔	✔	✘
	Core i7	High-end Performance	dual	✔	✔	✔	✔	✘
	Core i7	High-end Performance	quad	✔	✔	✔	✔	✘
	Xeon E3	Workstation/dense servers	quad	✔/✘	✔	✔	✔	✔

Release Dates

Skylake was first demonstrated at the 2014 Intel Developer Forum in San Francisco on September 9 with the goals of launching in the second half of 2015.

Process Technology

Main article: Broadwell § Process Technology

Skylake uses the same 14 nm process used for the Broadwell microarchitecture for all mainstream consumer parts (Core, Celeron, et al).

Compatibility

Vendor	OS	Version	Notes
Microsoft	Windows	Windows Vista	No Support
		Windows 7	Support ends July 2017
		Windows 8.1	Support ends July 2017
		Windows 10	Support
Linux	Linux	Kernel 3.19	Initial Support (MPX support)
Google	Chromium	Chromium	Support
Wind River	VxWorks	VxWorks 5.5?	Support

Compiler support

Compiler	Arch-Specific	Arch-Favorable
ICC	`-march=skylake`	`-mtune=skylake`
GCC	`-march=skylake`	`-mtune=skylake`
LLVM	`-march=skylake`	`-mtune=skylake`
Visual Studio	`/arch:AVX2`	`/tune:skylake`

CPUID

Core	Extended Family	Family	Extended Model	Model
Y/U	0	0x6	0x4	0xE
Y/U	Family 6 Model 78
DT/H/S	0	0x6	0x5	0xE
DT/H/S	Family 6 Model 94

Architecture

Overall Skylake builds upon Intel's previous microarchitecture, Broadwell, but includes a wider and more beefed up front end, more optimized execution engine, and numerous other enhancements. Intel designed Skylake to encompass a wide range of devices and applications with a large emphasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.

Key changes from Broadwell

8x performance/watt over Nehalem (Up from 3.5x in Haswell)
Mainstream chipset
- Lynx Point → Sunrise Point
- Bus/Interface to Chipset
  - DMI 3.0 (from 2.0)
    - Skylake S and Skylake H cores, connected by 4-lane DMI 3.0
    - Skylake Y and Skylake U cores have chipset in the same package (simplified OPIO)
    - Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane
    - Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
- PCIe & DMI upgraded to Gen3
- More I/O (configurable as PCIe/SATA/USB3)
- Lower-power I/O (eMMC, UFS, SDXC)
- CSI-2 for the integrated IPU (mobile SKUs)
- Intel Sensor Solution Hub integration
System Agent
- New Image Processing Unit (IPU)
  - Incorporates an image signal processor (ISP)
  - Mobile client models only
- Can now have its own variable voltage and frequency
Core
- Front End
  - Larger legacy pipeline delivery (5 µOPs, up from 4)
    - Another simple decoder has been added.
  - Allocation Queue (IDQ)
    - Larger delivery (6 µOPs, up from 4)
    - 2.28x larger buffer (64/thread, up from 56)
    - Partitioned for each active threads (from unified)
  - Improved branch prediction unit
    - reduced penalty for wrong direct jump target
    - No specifics were disclosed
  - µOP Cache
    - instruction window is now 64 Bytes (from 32)
    - 1.5x bandwidth (6 µOPs/cycle, up from 4)
- Execution Engine
  - Larger re-order buffer (224 entries, up from 192)
  - Larger scheduler (97 entries, up from 64)
    - Larger Integer Register File (180 entries, up from 168)
    - Larger Retire (4 µOPs/cycle/thread, up from 4 µOPs/cycle/core)?
- Memory Subsystem
  - Larger store buffer (56 entries, up from 42)
  - L2$ was changed from 8-way to 4-way set associative
  - Page split load penalty reduced 20-fold
  - Larger Write-back buffer
  - Larger Line Fill Buffer?

Memory
- Support for faster DDR-2400 memory
- L3$ re-gained 512 KiB/core (See §eDRAM architectural changes for the reason)
- A new coherent cache fabric implementation
  - doubles the throughput of the last level cache (LLC, L3$ in this case) miss handling
  - 50% improvement in bandwidth/watt
  - new eDRAM cache architecture for higher bandwidth
TLBs
- ITLB
  - 4 KiB page translations was changed from 4-way to 8-way associative
- STLB
  - 4 KiB + 2 MiB page translations was changed from 6-way to 12-way associative
Electrical
- The fully integrated voltage regulator (FIVR) is moved back to the motherboard
  - Originally intended to be a cost-cutting measure by moving the FIVR on-die as well as making it more efficient, the move resulted in unintentionally making the FIVR the limiting factor when it came to overclocking.
- DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals)
Testability
- New support for Direct Connect Interface (DCI), a new debugging transport protocol designed to allow debugging of closed cases (e.g. laptops, embedded) by accessing things such as JTAG through any USB 3 port.

Gen 9 GPUs
- Improved underlying implementation of the memory QoS for higher resolution displays and the integrated image signal processor (ISP)
  - Allow for higher concurrent bandwidth
- Skylake retires VGA support, multi-monitor support for up to 3 displays via HDMI 1.4, DP 1.2, and eDP 1.3 interfaces.
- Direct X 12, OpenCL 2.0, OpenGL 4.4
- Up to 24 EUs GT2 (same as Haswell); 48 EUs for GT3, and up to 72 EUs on Iris Pro Graphics
  - 1,152 GFLOPS @ 1 GHz

CPU changes

Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).
MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.
ADC and SBB have throughput of 1 op/cycle, same as Haswell.
Vector moves have throughput of 4 op/cycle (move elimination).
Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.
Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.
Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.
Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.
Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.
Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle.
vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op.
Throughput of some MMX ALU ops (such as PAND mm1, mm2) is decreased to 2 or 1 op/cycle (users are expected to use wider SSE/AVX registers instead).

New instructions

See also: Server Skylake's New instructions

Skylake introduced a number of new instructions:

SGX1 - Software Guard Extensions, Version 1
MPX -Memory Protection Extensions
XSAVEC - Save processor extended states with compaction to memory
XSAVES - Save processor supervisor-mode extended states to memory.
CLFLUSHOPT - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)

Block Diagram

Entire SoC Overview (dual)

Entire SoC Overview (quad)

Individual Core

Gen9

See Gen9#Gen9.

Memory Hierarchy

Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to Broadwell/Haswell.

Cache
- L0 µOP cache:
  - 1,536 µOPs, 8-way set associative
    - 32 sets, 6-µOP line size
    - statically divided between threads, per core, inclusive with L1I
- L1I Cache:
  - 32 KiB, 8-way set associative
    - 64 sets, 64 B line size
    - shared by the two threads, per core
- L1D Cache:
  - 32 KiB, 8-way set associative
  - 64 sets, 64 B line size
  - shared by the two threads, per core
  - 4 cycles for fastest load-to-use (simple pointer accesses)
    - 5 cycles for complex addresses
  - 64 B/cycle load bandwidth
  - 32 B/cycle store bandwidth
  - Write-back policy
- L2 Cache:
  - Unified, 256 KiB, 4-way set associative
  - 1024 sets, 64 B line size
  - Non-inclusive
  - 12 cycles for fastest load-to-use
  - 64 B/cycle bandwidth to L1$
  - Write-back policy
- L3 Cache/LLC:
  - Up to 2 MiB Per core, shared across all cores
  - Up to 16-way set associative
  - Inclusive
  - 64 B line size
  - Write-back policy
  - Per each core:
    - Read: 32 B/cycle (@ ring clock)
    - Write: 32 B/cycle (@ ring clock)
  - 42 cycles for fastest load-to-use
- Side Cache:
  - 64 MiB & 128 MiB eDRAM
  - Per package
  - Only on the Iris Pro GPUs
  - Read: 32 B/cycle (@ eDRAM clock)
  - Write: 32 B/cycle (@ eDRAM clock)
- System DRAM:
  - 2 Channels
  - 8 B/cycle/channel (@ memory clock)
  - 42 cycles + 51 ns latency

Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

TLBs:
- ITLB
  - 4 KiB page translations:
    - 128 entries; 8-way set associative
    - dynamic partitioning
  - 2 MiB / 4 MiB page translations:
    - 8 entries per thread; fully associative
    - Duplicated for each thread
- DTLB
  - 4 KiB page translations:
    - 64 entries; 4-way set associative
    - fixed partition
  - 2 MiB / 4 MiB page translations:
    - 32 entries; 4-way set associative
    - fixed partition
  - 1G page translations:
    - 4 entries; fully associative
    - fixed partition
- STLB
  - 4 KiB + 2 MiB page translations:
    - 1536 entries; 12-way set associative
    - fixed partition
  - 1 GiB page translations:
    - 16 entries; 4-way set associative
    - fixed partition

Overview

Skylake inherits much of the Core design philosophy which was enhanced significantly over the past number of architectures. Skylake, like its predecessor Broadwell, is also a dual-threaded and complex out-of-order pipeline. Skylake which builds on Broadwell incorporates large number of enhancements that has improved performance and efficiency in order to cover a large spectrum of devices from ultra-low power to high-performance computing. Additionally, a large number of improvements were done to the integrated graphics and multimedia capabilities as well as a new set of security technologies were introduced.

Design goals & new goals

Skylake tries to address 4 major design goals: Scalability, Performance, Power, and Media & Graphics. Skylake started out as a "traditional client product" when initial design goals and development started back in 2010. At that time, Skylake was expected to cover products ranging from thin-and-lights all the way up to desktops. This translated to roughly 3x TDP scale and 2x form factor between the smallest and biggest models. With the introduction of Ultralight, Skylake design goals were extended to a new class of smaller form factors (down to 15 W). Skylake design goals were later further extended to more mobility segments and even smaller form factors. The final end result is a microarchitecture that now spans 20-fold TDP scale (from 3.5 W all the way to 80 W+) and up to 4-fold form factor between the lowest power model and the highest performance model. Intel claims that Skylake also succeeded in reducing power by 40-60% during important workloads such as video, graphics, and idle power which especially affect models where battery life is absolutely critical.

It's interesting to note that Skylake's end result managed to overlap and to some degree exceed Intel's own ultra-low power (ULP) series of microarchitectures (i.e. Silvermont and Goldmont).

Product Development Vectors:

Form factor reduction - Emphasis was placed on reduction of form factor which includes both actual die size and package size.
Platform minimization - Effort was spent on reducing the overall platform size include reduction of system board size, components, and power.
Better life scenario power reduction - (mobile segment) The reduction of power during critical workloads such as video playback, video conferencing, and various other multimedia applications where the CPU itself is mostly idle.
IA performance - Improvements to both power and performance of the CPU core
IGP performance - Improvement to both power and performance of the GPU
New Security technology - Better protection against hardware and software attacks

SoC design

The Skylake system on a chip consists of a five major components: CPU core, LLC, Ring interconnect, System agent, and the integrated graphics. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. superset of features). Skylake features an improved core (see § Pipeline) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically dual-core while mainstream desktop models are typically quad-core with dual-core desktop models still offered for value models (e.g. Celeron). Accompanying the cores is the LCC (last level cache or L3$ as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth.

Accompanying the cores is the Gen9 integrated graphics unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 (Gen9 § Pipeline) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated eDRAM ranging from 64 GiB to 120 GiB in capacity. The eDRAM is packaged along with the SoC in the same package.

On the other side is the System Agent (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded integrated memory controller (IMC) with most mainstream models supporting faster memory and dual-channel DDR4. The SA in Skylake also includes the Display Controller which now supports higher resolution displays with up to three displays for all mainstream models.

The SA also incorporates up to 20 lanes of PCIe with lesser amounts depending on the model. Of the 20 lanes, x16 PCIe lanes are offered for an external dedicated graphics hookup with the other four lanes reserved for communication with the southbridge chipset over Intel's new proprietary DMI 3.0 bus. The upgrade from DMI 2.0 (used in previous architectures) to 3.0 increased the bandwidth by 60% (8.0 GT/s from 5). For some models where form factor is exceptionally critical, such as those used for ultralight device, the chipset is packaged along with the SoC utilizing an on-package-interconnect (OPI) instead.

The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an image signal processor (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer.

Core

Overview

Skylake shares most of the development vectors with its predecessor while introducing a one of new constraint. The overall goals were:

Performance improvements - the traditional way of milking more performance by increasing the instructions per cycle as well as clock frequency.
Power efficiency - reduction of power for all functional blocks
Security enhancements - new security features are implemented in hardware in the core
Configurability

Configurability

Intel has been experiencing a growing divergence in functionality over the last number of iterations of their microarchitecture between their mainstream consumer products and their high-end HPC/server models. Traditionally, Intel has been using the same exact core design for everything from their lowest end value models (e.g. Celeron) all the way up to the highest-performance enterprise models (e.g. Xeon E7). While the two have fundamentally different chip architectures, they use the same exact CPU core architecture as the building block.

This design philosophy has changed with Skylake. In order to better accommodate the different functionalities of each segment without sacrificing features or making unnecessary compromises Intel went with a configurable core. The Skylake core is a single development project, making up a master superset core. The project result in two derivatives: one for servers and one for clients (the topic of this article). All mainstream models (from Celeron/Pentium all the way up to Core i7/Xeon E3) use the client core configuration. Server models (e.g. Xeon Gold/Xeon Platinum) will be using the new server configuration.

The server core is considerably larger than the client one, featuring Advanced Vector Extensions 512 (AVX-512). Skylake servers support what was formerly called AVX3.2 (AVX512F + AVX512CD + AVX512BW + AVX512DQ + AVX512VL). Additionally, those processors Memory Protection Keys for Userspace (PKU), PCOMMIT, and CLWB.

Pipeline

The Skylake core focuses on extracting performance and reducing power through a number of key ways. Intel builds Skylake on previous microarchitectures, descendants of Sandy Bridge. For the core to increase the overall performance, Intel focused on extracting additional parallelism.

Broad Overview

At a 5,000 foot view, Skylake represents the logical evolution from Haswell and Broadwell. Therefore, despite some significant differences from the previous microarchitecture, the overall designs is fundamentally the same and can be seen as enhancements over Broadwell rather than a complete change.

The pipeline can be broken down into three areas: the front-end, back-end or execution engine, and the memory subsystem. The goal of the front-end is to feed the back-end with a sufficient stream of operations which it gets by decoding instructions coming from memory. The front-end has two major pathways: the µOPs cache path and the legacy path. The legacy path is the traditional path whereby variable-length x86 instructions are fetched from the level 1 instruction cache, queued, and consequently get decoded into simpler, fixed-length µOPs. The alternative and much more desired path is the µOPs cache path whereby a cache containing already decoded µOPs receives a hit allowing the µOPs to be sent directly to the decode queue.

Regardless of which path an instruction ends up taking it will eventually arrive at the decode queue. The IDQ represents the end of the front-end and the in-order part of the machine and the start of the execution engine which operates out-of-order.

In the back-end, the micro-operations visit the reorder buffer. It's there where register allocation, renaming, and retiring takes place. At this stage a number of other optimizations are also done. From the reorder buffer, µOPs are sent to the unified scheduler. The scheduler has a number of exit ports, each wired to a set of different execution units. Some units can perform basic ALU operations, others can do multiplication and division, with some units capable of more complex operations such as various vector operations. The scheduler is effectively in charge of queuing the µOPs on the appropriate port so they can be executed by the appropriate unit.

Some µOPs deal with memory access (e.g. load & store). Those will be sent on dedicated scheduler ports that can perform those memory operations. Store operations go to the store buffer which is also capable of performing forwarding when needed. Likewise, Load operations come from the load buffer. Skylake features a dedicated 32 KiB level 1 data cache and a dedicated 32 KiB level 1 instruction cache. It also features a core-private 256 KiB L2 cache that is shared by both of the L1 caches.

Each core enjoys a slice of a third level of cache that is shared by all the core. In the client configuration for Skylake, there are either two cores or four cores connected while in the server configuration, up to 28 cores may be hooked together on a single chip.

Front-end

The front-end is is tasked with the challenge of fetching the complex x86 instructions from memory, decoding them, and delivering them to the execution units. In other words, the front end needs to be able to consistently deliver enough µOPs from the instruction code stream to keep the back-end busy. When the back-end is not being fully utilized, the core is not reaching its full performance. A poorly or under-performing front-end will translate directly to a poorly performing core. This challenge is further complicated by various redirection such as branches and the complex nature of the x86 instructions themselves.

Fetch & pre-decoding

On their first pass, instructions should have already been prefetched from the L2 cache and into the L1 cache. The L1 is a 32 KiB, 8-way set associative cache, identical in size and organization to previous generations. Skylake fetching is done on a 16-byte fetch window. A window size that has not changed in a number of generations. Up to 16 bytes of code can be fetched each cycle. Note that fetcher is shared evenly between two thread, so that each thread gets every other cycle. At this point they are still macro-ops (i.e. variable-length x86 architectural instruction). Instructions are brought into the pre-decode buffer for initial preparation.

x86 instructions are complex, variable length, have inconsistent encoding, and may contain multiple operations. At the pre-decode buffer the instructions boundaries get detected and marked. This is a fairly difficult task because each instruction can vary from a single byte all the way up to fifteen. Moreover, determining the length requires inspecting a couple of bytes of the instruction. In addition boundary marking, prefixes are also decoded and checked for various properties such as branches. As with previous microarchitectures, the pre-decoder has a throughput of 6 macro-ops per cycle or until all 16 bytes are consumed, whichever happens first. Note that the predecoder will not load a new 16-byte block until the previous block has been fully exhausted. For example, suppose a new chunk was loaded, resulting in 7 instructions. In the first cycle, 6 instructions will be processed and a whole second cycle will be wasted for that last instruction. This will produce the much lower throughput of 3.5 instructions per cycle which is considerably less than optimal. Likewise, if the 16-byte block resulted in just 4 instructions with 1 byte of the 5th instruction received, the first 4 instructions will be processed in the first cycle and a second cycle will be required for the last instruction. This will produce an average throughput of 2.5 instructions per cycle. Note that there is a special case for length-changing prefix (LCPs) which will incur additional pre-decoding costs. Real code is often less than 4 bytes which usually results in a good rate.

All of this works along with the branch prediction unit which attempts to guess the flow of instructions. In Skylake, the branch predictor has also been improved. The branch predictor now has reduced penalty (i.e. lower latency) for wrong direct jump target prediction. Additionally, the predictor in Skylake can inspect further in the byte stream than in previous architectures. The intimate improvements done in the branch predictor were not further disclosed by Intel.

Instruction Queue & MOP-Fusion

MOP-Fusion Example:
cmp eax, [mem] jne loop	→	cmpjne eax, [mem], loop

See also: Macro-Operation Fusion

The pre-decoded instructions are delivered to the Instruction Queue (IQ). In Broadwell, the Instruction Queue has been increased to 25 entries duplicated over for each thread (i.e. 50 total entries). It's unclear if that has changed with Skylake. One key optimization the instruction queue does is macro-op fusion. Skylake can fuse two macro-ops into a single complex one in a number of cases. In cases where a test or compare instruction with a subsequent conditional jump is detected, it will be converted into a single compare-and-branch instruction. Those fused instructions remain fused throughout the entire pipeline and get executed as a single operation by the branch unit thereby saving bandwidth everywhere. Only one such fusion can be performed each cycle.

Decoding

Up to five pre-decoded instructions are sent to the decoders each cycle. Like the fetchers, the Decoders alternate between the two thread each cycle. Decoders read in macro-operations and emit regular, fixed length µOPs. Skylake represents a big genealogical change from the last couple of microarchitectures. Skylake's pipeline is wider than it predecessors; Skylake adds another simple decoder. The five decoders are asymmetric; the first one, Decoder 0, is a complex decoder while the other four are simple decoders. A simple decoder is capable of translating instructions that emit a single fused-µOP. By contrast, a complex decoder can decode anywhere from one to four fused-µOPs. Skylake is now capable of decoding 5 macro-ops per cycle or 25% more than Broadwell, however this does not translates directly to direct IPC uplift to due to various other more restricting points in the pipeline. Intel chose not increase the number of complex decoders because it's much harder to extract additional parallelism from the µOPs emitted by a complex instruction. Overall up to 5 simple instructions can be decoded each cycle with lesser amounts if the complex decoder needs to emit addition µOPs; i.e., for each additional µOP the complex decoder needs to emit, 1 less simple decoder can operate. In other words, for each additional µOP the complex decoder emits, one less decoder is active.

MSROM & Stack Engine

There are more complex instructions that are not trivial to be decoded even by complex decoder. For instructions that transform into more than four µOPs, the instruction detours through the microcode sequencer (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode sequencer is done. During that time, the decoders are disabled.

x86 has dedicated stack machine operations. Instructions such as PUSH, POP, as well as CALL, and RET all operate on the stack pointer (ESP). Without any specialized hardware, such operations would would need to be sent to the back-end for execution using the general purpose ALUs, using up some of the bandwidth and utilizing scheduler and execution units resources. Since Pentium M, Intel has been making use of a Stack Engine. The Stack Engine has a set of three dedicated adders it uses to perform and eliminate the stack-updating µOPs (i.e. capable of handling three additions per cycle). Instruction such as PUSH are translated into a store and a subtraction of 4 from ESP. The subtraction in this case will be done by the Stack Engine. The Stack Engine sits after the decoders and monitors the µOPs stream as it passes by. Incoming stack-modifying operations are caught by the Stack Engine. This operation alleviate the burden of the pipeline from stack pointer-modifying µOPs. In other words, it's cheaper and faster to calculate stack pointer targets at the Stack Engine than it is to send those operations down the pipeline to be done by the execution units (i.e., general purpose ALUs).

µOP cache & x86 tax

Decoding the variable-length, inconsistent, and complex x86 instructions is a nontrivial task. It's also expensive in terms of performance and power. Therefore, the best way for the pipeline to avoid those things is to simply not decode the instructions. This is the job of the µOP cache or the Decoded Stream Buffer (DSB). Skylake's µOP cache is organized similarly to previous generations like Sandy Bridge, however both the bandwidth and the tracking window was increased. The cache is organized into 32 sets of 8 cache lines with each line holding up to 6 µOP for a total of 1,536 µOPs. Whereas previously (e.g. Haswell) the µOP cache operated on 32-byte windows, in Skylake the window size has been doubled to 64-bytes. The micro-operation cache is competitively shared between the two threads and can also hold pointers to the microcode. The µOP cache has an average hit rate of 80%.

A hit in the µOP allows for up to 6 µOP (i.e., entire line) per cycle to be sent directly to the Instruction Decode Queue (IDQ), bypassing all the pre-decoding and decoding that would otherwise have to be done. Whereas the legacy decode path works in 16-byte instruction fetch windows, the µOP cache has no such restriction and can deliver 6 µOP/cycle corresponding to the much bigger 64-byte window. Previously (e.g., Broadwell), the bandwidth was lower at 4 µOP per cycle. The 1.5x bandwidth increase greatly improves the numbers of µOP that the back-end can take advantage of in the out-of-order part of the machine.

Allocation Queue

The emitted µOPs from the decoders are sent directly to the Allocation Queue (AQ) or Instruction Decode Queue (IDQ). The Allocation Queue acts as the interface between the front-end (in-order) and the back-end (out-of-order). Skylake's Allocation Queue has more than doubled from Broadwell from 28-entries per thread to 64-entries per thread. Unlike in Haswell, the IDQ is no longer competitively shared; it's partitioned between two active threads. The queue's purpose is effectively help absorb bubbles which may be introduced in the front-end, ensuring that a steady stream of 6 µOPs are delivered each cycle.

µOP-Fusion & LSD

The IDQ does a number of additional optimizations as it queues instructions. The Loop Stream Detector (LSD) is a mechanism inside the IDQ capable of detecting loops that fit in the IDQ and lock them down. That is, the LSD can stream the same sequence of µOPs directly from the IDQ continuously without any additional fetching, decoding, or utilizing additional caches or resources. Streaming continues indefinitely until reaching a branch mis-prediction. Note that while the LSD is active, the rest of the front-end is effectively disabled.

The LSD in Skylake can take advantage of the considerably larger IDQ; capable of detecting loops up to 64 µOPs per thread. The LSD is particularly excellent in for many common algorithms that are found in many programs (e.g., tight loops, intensive calc loops, searches, etc..).

NOTE: A microcode update appear to have disabled the LSD on client processors. See {{\\|skylake_(server)#Front-end_2|Skylake (server) § Server Front-end]].

Execution engine

Skylake's back-end or execution engine deals with the execution of out-of-order operations. Much of the design is inherited from previous architectures such as Haswell but has been widened to explorer more instruction-level parallelism opportunities. From the allocation queue instructions are sent to the Reorder Buffer (ROB) at the rate of up to 6 fused-µOPs each cycle. Skylake's throughput is up by 2 fused-µOPs per cycle from Broadwell in order to accommodate the wider front-end.

Renaming & Allocation

Like the front-end, the Reorder Buffer has been increased to 224 entries, 32 entries more than Broadwell. It is at this stage that architectural registers are mapped onto the underlying physical registers. Other additional bookkeeping tasks are also done at this point such as allocating resources for stores, loads, and determining all possible scheduler ports. Register renaming is also controlled by the Register Alias Table (RAT) which is used to mark where the data we depend on is coming from (after that value, too, came from an instruction that has previously been renamed). In previous microarchitectures, the RAT could handle 4 µOPs each cycle. Intel has not disclosed if that has changed in Skylake but it's possible. If this has not change, Skylake can rename any four registers per cycle. This includes the same register renamed four times in a single cycle. If the rename has not increased in Skylake, some aspects of improvements that were done in the prefetch/decode stages are effectively lost. Note that the ROB still operates on fused µOPs, therefore 4 µOPs can effectively be as high as 8 µOPs.

It should be noted that there is no special costs involved in splitting up fused µOPs before execution or retirement and the two fused µOPs only occupy a single entry in the ROB.

Since Skylake performs speculative execution, it can speculate incorrectly. When this happens, the architectural state is invalidated and as such needs to be rolled back to the last known valid state. Skylake has a 48-entry Branch Order Buffer (BOB) that keeps tracks of those states for this very purpose.

Optimizations

Skylake as a number of optimizations it performs prior to entering the out-of-order and renaming part. Three of those optimizations include Move Elimination and Zeroing Idioms, and Ones Idioms. A Move Elimination is capable of eliminating register-to-register moves (including chained moves) prior to bookkeeping at the ROB, allowing those µOPs to save resources and eliminating them entirely. Eliminated moves are zero latency and are entirely removed from the pipeline. This optimization does not always succeed; when it fails, the operands were simply not ready. On average this optimization is almost always successful (upward of 85% in most cases). Move elimination works on all 32- and 64-bit GP integer registers as well as all 128- and 256-bit vector registers.

Zeroing Idiom Example:

xor eax, eax

Not only does this instruction get eliminated at the ROB, but it's actually encoded as just 2 bytes 31 C0 vs the 4 bytes for mov eax, 0x0 which is encoded as b8 00 00 00 00.

There are some exceptions that Skylake will not optimize, most dealing with signedness. sign-extended moves cannot be eliminated and neither can zero-extended from 16-bit to 32/64 big registers (note that 8-bit to 32/64 works). Likewise, in the other direction, no moves to 8/16-bit registers can be eliminated. A move of a register to itself is never eliminated.

When instructions use registers that are independent of their prior values, another optimization opportunity can be exploited. A second common optimization performed in Skylake around the same time is Zeroing Idioms elimination. A number common zeroing idioms are recognized and consequently eliminated in much the same way as the move eliminations are performed. Skylake recognizes instructions such as XOR, PXOR, and XORPS as zeroing idioms when the source and destination operands are the same. Those optimizations are done at the same rate as renaming during renaming (at 4 µOPs per cycle) and the register is simply set to zero.

The ones idioms is another dependency breaking idiom that can be optimized. In all the various PCMPEQx instructions that perform packed comparison the same register with itself always set all bits to one. On those cases, while the µOP still has to be executed, the instructions may be scheduled as soon as possible because all the decencies are resolved.

Scheduler

The scheduler itself was increased by 50%; with up to 97 entries (from 64 in Broadwell) being competitively shared between the two threads. Skylake continues with a unified design; this is in contrast to designs such as AMD's Zen which uses a split design each one holding different types of µOPs. Scheduler includes the two register files for integers and vectors. It's in those register files that output operand data is store. In Skylake, the integer register file was also slightly increased from 160 entries to 180.

At this point µOPs are not longer fused and will be dispatched to the execution units independently. The scheduler holds the µOPs while they wait to be executed. A µOP could be waiting on an operand that has not arrived (e.g., fetched from memory or currently being calculated from another µOPs) or because the execution unit it needs is busy. Once the µOP is ready, they are dispatched through their designated port. The scheduler will send the oldest ready µOP to be executed on each of the eight ports each cycle.

The scheduler had its ports rearranged to better balance various instructions. For example, divide and sqrt instructions latency and throughput were improved. The latency and throughput of floating point ADD, MUL, and FMA were made uniformed at 4 cycles with a throughput of 2 µOPs/clock. Likewise the latency of AES instructions were significantly reduced from 7 cycles down to 4.

Scheduler Ports & Execution Units

Scheduler Ports Designation
Port 0	Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops
	FP Add, Multiply, FMA
	Integer/FP Division and Square Root
	AES Encryption
	Branch2
Port 1	Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning
Port 1	FP Add, Multiply, FMA
Port 5	Integer/Vector Arithmetic, Logic
	Vector Permute
	x87 FP Add, Composite Int, CLMUL
Port 6	Integer Arithmetic, Logic, Shift
Port 6	Branch
Port 2	Load, AGU
Port 3	Load, AGU
Port 4	Store, AGU
Port 7	AGU

Execution Units
Execution Unit	# of Units	Instructions
ALU	4	add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap, (v)movup
DIV	1	divp, divs, vdiv, sqrt, vsqrt, rcp, vrcp, rsqrt, idiv
Shift	2	sal, shl, rol, adc, sarx, adcx, adox, etc...
Shuffle	1	(v)shufp, vperm, (v)pack, (v)unpck, (v)punpck, (v)pshuf, (v)pslldq, (v)alignr, (v)pmovzx, vbroadcast, (v)pslldq, (v)psrldq, (v)pblendw
Slow Int	1	mul, imul, bsr, rcl, shld, mulx, pdep, etc...
Bit Manipulation	2	andn, bextr, blsi, blsmsk, bzhi, etc
FP Mov	1	(v)movsd/ss, (v)movd gpr
SIMD Misc	1	STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
Vec ALU	3	(v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap, (v)movup, (v)andp, (v)orp, (v)paddb/w/d/q, (v)blendv, (v)blendp, (v)pblendd
Vec Shift	2	(v)psllv, (v)psrlv, vector shift count in imm8
Vec Add	2	(v)addp, (v)cmpp, (v)max, (v)min, (v)padds, (v)paddus, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
Vec Mul	2	(v)mul, (v)pmul, (v)pmadd*
This table was taken verbatim from the Intel manual. Execution unit mapping to MMX instructions are not included.

Retirement

Once a µOP executes, or in the case of fused µOPs both µOPs have executed, they can be retired. Haswell is able to commit up to four fused µOPs each cycle per thread. Retirement happens in-order and releases any used resources such as those used to keep track in the reorder buffer. Because the allocation queue delivery in Skylake has been increased to 6 µOPs (12 unfused) from previously 4 µOPs (8 unfused) per cycle, the SMT implementation in Skylake should have some additional efficiency as there's now better chance for higher sustainable retirement rate.

Memory subsystem

Skylake's memory subsystem is in charge of the loads and store requests and ordering. Since Haswell, it's possible to sustain two memory reads (on ports 2 and 3) and one memory write (on port 4) each cycle. Each memory operation can be of any register size up to 256 bits. Skylake memory subsystem has been improved. The store buffer has been increased by 42 entries from Broadwell to 56 for a total of 128 simultaneous memory operations in-flight or roughly 60% of all µOPs. Special care was taken to reduce the penalty for page-split loads; previously scenarios involving page-split loads were thought to be rarer than they actually are. This was addressed in Skylake with page-split loads are now made equal to other splits loads. Expect page split load penalty down to 5 cycles from 100 cycles in Broadwell. The average latency to forward a load to store has also been improved and stores that miss in the L1$ generate L2$ requests to the next level cache much earlier in Skylake than before.

The L2 to L1 bandwidth in Skylake is the same as Haswell at 64 bytes per cycle in either direction. Note that one operation can be done each cycle; i.e., the L1 can either receive data from the L1 or send data to the Load/Store buffers each cycle, but not both. Latency from L2$ to L3$ has also been increased from 4 cycles/line to 2 cycles/line. The bandwidth from the level 2 cache to the shared level 3 is 32 bytes per cycle.

eDRAM architectural changes

Intel ships a number of products with Embedded DRAM incorporated on package in order to increase performance of the integrated graphics and to a lesser degree the code through additional bandwidth and caching. There has been a number of significant architectural changes in how the eDRAM works in Skylake.

In Broadwell, the eDRAM was statically attached to the LLC (last level cache, L3$ from the perspective of the CPU Cores and L4$ from the perspective of the IGP), effectively stealing half a Mebibyte per core in the process, but behaving as an architectural true level 4 cache. This was fundamentally changed in Skylake. In Skylake, Intel removed the eDRAM from the LLC to its own array, re-freeing the 512 KiB (hence the 1.5 MiB/core in Broadwell and 2 MiB back in Skylake), but also removing the undesired dependency between the capacity of the eDRAM and the number of cores. Skylake's cache is effectively no longer a true level 4 cache but rather a memory side cache. This has a number of benefits such as that each and every memory access that goes through the memory controller gets looked up in the eDRAM. On a satisfied hit, the value is obtained from there. On a miss, a value gets allocated and stored in the eDRAM (subject to a number of restrictions, for example no I/O devices requests get cached on the eDRAM).

Skylake vs Broadwell eDRAM Architecture
Broadwell	Skylake

The new eDRAM changes mean it's no longer architectural - capable of caching any data (including "unreachable memory", display engines, and effectively any memory transfer not bound by software restrictions) and is entirely invisible to software (one exception noted later) in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performance, the graphics driver may decide to limit certain memory accesses to only the eDRAM, only the LLC, or in both of them.