• intel/microarchitectures/cannon lake
  | Fin Pitch ||  42 nm ||  34 nm || 0.81x | Gate Pitch ||  70 nm ||  54 nm || 0.77x
  7 KB (887 words) - 12:53, 5 August 2019
• 40 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  2 KB (182 words) - 03:11, 17 August 2023
• 65 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  4 KB (407 words) - 05:55, 20 July 2018
• 130 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  5 KB (500 words) - 16:02, 13 May 2020
• 90 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  3 KB (354 words) - 03:09, 17 August 2023
• 180 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  4 KB (413 words) - 03:04, 17 August 2023
• 10 nm lithography process
  ...a certain size and its technology, as opposed to [[gate length]] or [[half pitch]]. The 10 nm node is currently being introduced and is set to get replaced ...ypically have a [[gate pitch]] in range of 50-60s nm and a [[minimum metal pitch]] in the range of 30-40s nm. Due to the small feature sizes, for the [[crit
  14 KB (1,903 words) - 06:52, 17 February 2023
• 7 nm lithography process
  ...a fourth-generation [[FinFET]], fifth-generation [[HKMG]], gate-last, dual gate oxide process. ...ate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the [[SADP]] point
  13 KB (1,941 words) - 02:40, 5 November 2022
• 5 nm lithography process
  [[File:N5 mx rc and vx rc.png|right|thumb|200px|Tightest pitch Mx RC and Vx RC on 5nm was kept at similar levels to N7.]] ...r to reduce cell spacing. Additionally, TSMC added the ability to drop the gate contact over the active region (COAG). Although originally experimented wit
  11 KB (1,662 words) - 02:58, 2 October 2022
• 250 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  6 KB (661 words) - 16:18, 21 August 2022
• 350 nm lithography process
  |Gate Oxide |Contacted Gate Pitch
  5 KB (586 words) - 22:44, 4 April 2022
• 500 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  4 KB (438 words) - 06:15, 20 July 2018
• 600 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  1 KB (145 words) - 06:15, 20 July 2018
• 650 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  1 KB (131 words) - 06:15, 20 July 2018
• 1.2 µm lithography process
  |Gate Length |Interconnect Pitch (M1P)
  962 bytes (118 words) - 23:04, 20 May 2018
• 1.3 µm lithography process
  |Gate Length |Interconnect Pitch (M1P)
  1 KB (138 words) - 12:57, 23 October 2022
• 110 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  1 KB (143 words) - 05:57, 20 July 2018
• 150 nm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  2 KB (238 words) - 02:56, 27 September 2020
• 7 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch
  710 bytes (91 words) - 06:15, 18 January 2022
• 3.5 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch
  1 KB (122 words) - 06:21, 20 July 2018

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