Semiconductor & Computer Engineering
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Difference between revisions of "lake"
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[[File:sunny cove roadmap.png]] | [[File:sunny cove roadmap.png]] | ||
| − | + | == See also == | |
| − | :;[[Intel]] • {{intel|CPUID}} | + | :;[[Intel]] • {{intel|CPUID}} • [[intel/roadmap|Roadmap]] |
*{{intel|Atom}} | *{{intel|Atom}} | ||
*{{intel|Core|l=arch}} | *{{intel|Core|l=arch}} | ||
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*{{intel|Xeon}} | *{{intel|Xeon}} | ||
*[[Lake]] | *[[Lake]] | ||
| + | ---- | ||
| + | {| border="0" cellpadding="2" width="100%" | ||
| + | |- | ||
| + | |width="29%" valign="top" align="left"| | ||
| + | {{intel ice lake core see also}} | ||
| + | |width="29%" valign="top" align="left"| | ||
| + | {{intel cascade lake core see also}} | ||
| + | * '''{{intel|Comet Lake|l=arch}}''' | ||
| + | * '''{{intel|Rocket Lake|l=arch}}''' | ||
| + | |width="42%" valign="top" align="left"| | ||
| + | {{intel kaby lake core see also}} | ||
| + | * '''{{intel|Cooper Lake|l=arch}}''' | ||
| + | ** {{intel|Cooper Lake SP|l=core}} | ||
| + | |} | ||
| + | ---- | ||
| + | {| border="0" cellpadding="2" width="100%" | ||
| + | |- | ||
| + | |width="29%" valign="top" align="left"| | ||
| + | {{intel skylake core see also}} | ||
| + | |width="29%" valign="top" align="left"| | ||
| + | {{intel broadwell core see also}} | ||
| + | |width="42%" valign="top" align="left"| | ||
| + | {{intel cannon lake core see also}} | ||
| + | |} | ||
| + | ---- | ||
| + | {| border="0" cellpadding="2" width="100%" | ||
| + | |- | ||
| + | |width="29%" valign="top" align="left"| | ||
| + | {{intel alder lake core see also}} | ||
| + | * '''{{intel|Tiger Lake|l=arch}}''' | ||
| + | * '''{{intel|Raptor Lake|l=arch}}''' | ||
| + | * '''{{intel|Meteor Lake|l=arch}}''' | ||
| + | |width="29%" valign="top" align="left"| | ||
| + | {{intel sandy bridge core see also}} | ||
| + | * '''{{intel|Ivy Bridge|l=arch}}''' | ||
| + | ** {{intel|Ivy Bridge E|l=core}} | ||
| + | ** {{intel|Ivy Bridge M|l=core}} | ||
| + | |width="42%" valign="top" align="left"| | ||
| + | {{intel coffee lake core see also}} | ||
| + | |} | ||
{{disambig}} | {{disambig}} | ||
Latest revision as of 23:18, 13 May 2025
Overview[edit]
Lake may refer to:
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Intel CPU Core Roadmap[edit]
- See also: Intel Atom and intel/core
| Intel Atom (ULV) | Node name | Intel Core/Pentium | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Microarch | Core/Step | Microarch | Core/Step | |||||||||
| 600 nm | P6 | Pentium Pro (133 MHz) |
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| 500 nm | Pentium Pro (150 MHz) |
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| 350 nm | Pentium Pro (166–200 MHz) |
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| Klamath | ||||||||||||
| 250 nm | Deschutes | |||||||||||
| Katmai | NetBurst | |||||||||||
| 180 nm | Coppermine | Willamette (P4) | ||||||||||
| 130 nm | Tualatin | Northwood (P4) | ||||||||||
| Pentium M | Banias | NetBurst (HT) | NetBurst (×2) | |||||||||
| 90 nm | Dothan | Prescott (P4) | ⇨ | Prescott‑2M | ⇨ | Smithfield | ||||||
| → | ⇩ | → | ||||||||||
| 65 nm | Yonah | Cedar Mill (P4) | ⇨ | Presler | ||||||||
| Core | Merom | 4 cores on mainstream desktop, DDR3 introduced | ||||||||||
| Bonnell | Bonnell | 45 nm | Penryn | |||||||||
| Nehalem | Nehalem | Hyper-threading reintroduced, integrated Memory controller, PCH, L3-cache introduced, 256KB L2-cache/core |
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| Saltwell | 32 nm | Westmere | Introduced GPU on same package and AES-NI | |||||||||
| Sandy Bridge | Sandy Bridge | On-die ring bus, no more non-UEFI motherboards | ||||||||||
| Silvermont | Silvermont | 22 nm | Ivy Bridge | |||||||||
| Haswell | Haswell | Fully integrated voltage regulator | ||||||||||
| Airmont | 14 nm | Broadwell | ||||||||||
| Skylake | Skylake | DDR4 introduced on mainstream desktop | ||||||||||
| Goldmont | Goldmont | Kaby Lake | ||||||||||
| Coffee Lake | 6 cores on mainstream desktop | |||||||||||
| Amber Lake | Mobile-only | |||||||||||
| Goldmont Plus | Goldmont Plus | Whiskey Lake | Mobile-only | |||||||||
| Coffee Lake Refresh | 8 cores on mainstream desktop | |||||||||||
| Comet Lake | 10 cores on mainstream desktop | |||||||||||
| Rocket Lake | Cypress Cove | Backported Sunny Cove microarchitecture for 14nm | ||||||||||
| Tremont | Tremont (Lakefield) |
10 nm | Cannon Lake | Palm Cove | Mobile-only | |||||||
| Ice Lake | Sunny Cove | 512 KB L2-cache/core | ||||||||||
| Tiger Lake | Willow Cove | Intel Xe graphics engine | ||||||||||
| Gracemont | Gracemont | Intel 7 (10nm ESF) |
Alder Lake | Golden Cove | Hybrid, DDR5, PCIe 5.0 | |||||||
| Raptor Lake | Raptor Cove | |||||||||||
| Crestmont | Crestmont | Intel 4 | Meteor Lake | Redwood Cove | Mobile-only, NPU, chiplet architecture | |||||||
| Skymont | Skymont | N3B (TSMC) | Lunar Lake | Lion Cove | Low power mobile only (9-30W) | |||||||
| Arrow Lake | Lion Cove | |||||||||||
| Darkmont | Darkmont | 18A | Panther Lake | Cougar Cove | ||||||||
}}
See also[edit]
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This is a disambiguation page used to distinguish between articles with similar names. If an internal link led you here, you may wish to change the link to point directly to the intended article. |