From WikiChip
Difference between revisions of "intel/cpuid"
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! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model | ! Microarchitecture !! Core !! Extended <br>Family !! Family !! Extended <br>Model !! Model !! Family • Model | ||
|- | |- | ||
− | | colspan="7" | • ''"Hybrid" Processors (P-Core/E-Core)'' • | + | | colspan="7" | • ''"Hybrid" Processors (P-[[Core]]/E-[[Core]])'' • [[Intel]] [[Core]] • [[Intel Atom]] |
|- | |- | ||
! {{intel|Razer Lake|l=arch}} ([[2027]]) | ! {{intel|Razer Lake|l=arch}} ([[2027]]) | ||
Line 294: | Line 294: | ||
:Raptor Lake-S, Raptor Lake-U, Raptor Lake-P, Raptor Lake-PX, Raptor Lake-H, Raptor Lake-HX --> | :Raptor Lake-S, Raptor Lake-U, Raptor Lake-P, Raptor Lake-PX, Raptor Lake-H, Raptor Lake-HX --> | ||
! rowspan="3" | {{intel|Bartlett Lake|l=arch}} ([[2025]])<br><small>(Raptor Lake Refresh)</small> | ! rowspan="3" | {{intel|Bartlett Lake|l=arch}} ([[2025]])<br><small>(Raptor Lake Refresh)</small> | ||
− | | {{intel|Raptor Cove|l=core}} (P) • U | + | | {{intel|Raptor Cove|l=core}} (P) • U • H <hr>''{{intel|Gracemont|l=arch}}'' (E) • {{intel|Bartlett Lake N|BLL-N|l=core}} || 0 || 0x6 || 0xB || 0xF<hr>''0xE'' || [[Family 6 Model 191]] ?<hr>[[Family 6 Model 190]] ? |
|- | |- | ||
− | | {{intel|Raptor Cove|l=core}} (P) • | + | | {{intel|Raptor Cove|l=core}} (P) • {{intel|Bartlett Lake P|BLL-P|l=core}} || 0 || 0x6 || 0xB || 0xA || [[Family 6 Model 186]] |
|- | |- | ||
− | | {{intel|Raptor Cove|l=core}} (P) • | + | | {{intel|Raptor Cove|l=core}} (P) • {{intel|Bartlett Lake S|BLL-S|l=core}} <br>Enhanced ''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0xB || 0x7 || [[Family 6 Model 183]] |
|- <!-- Core Ultra 200V; Lion Cove P-cores and Skymont E-core • 000B06D1 • 4C+4C Intel Core Ultra 9 288V @4200MHz (Lunar Lake-MX, Lion Cove + Skymont), top SKU --> | |- <!-- Core Ultra 200V; Lion Cove P-cores and Skymont E-core • 000B06D1 • 4C+4C Intel Core Ultra 9 288V @4200MHz (Lunar Lake-MX, Lion Cove + Skymont), top SKU --> | ||
! {{intel|Lunar Lake|l=arch}} ([[2024]]) | ! {{intel|Lunar Lake|l=arch}} ([[2024]]) | ||
− | | • LNL-MX | + | | • LNL-V • LNL-MX <hr>{{intel|Lion Cove|l=core}} (P) <br>{{intel|Skymont}} (E/LPE) || 0 || 0x6 || 0xB || 0xD<hr>0xC || [[Family 6 Model 189]] ? BD<hr>[[Family 6 Model 188]] ? BC |
|- <!-- Core Ultra 200U; Lion Cove P-cores and Skymont E-core • 2P+8E+2LPE • Intel 3 • LGA2049 --> | |- <!-- Core Ultra 200U; Lion Cove P-cores and Skymont E-core • 2P+8E+2LPE • Intel 3 • LGA2049 --> | ||
! rowspan="3" | {{intel|Arrow Lake|l=arch}} ([[2024]]) | ! rowspan="3" | {{intel|Arrow Lake|l=arch}} ([[2024]]) | ||
Line 317: | Line 317: | ||
:RAPTORLAKE • IFM(6, 0xB7); RAPTORLAKE_P • IFM(6, 0xBA); RAPTORLAKE_S • IFM(6, 0xBF) ! --> | :RAPTORLAKE • IFM(6, 0xB7); RAPTORLAKE_P • IFM(6, 0xBA); RAPTORLAKE_S • IFM(6, 0xBF) ! --> | ||
! rowspan="3" | {{intel|Raptor Lake|l=arch}} ([[2022]]) | ! rowspan="3" | {{intel|Raptor Lake|l=arch}} ([[2022]]) | ||
− | | {{intel|Raptor Cove|l=core}} (P) • U | + | | {{intel|Raptor Cove|l=core}} (P) • U • H <hr>''{{intel|Gracemont|l=arch}}'' (E) • {{intel|Raptor Lake N|RPL-N|l=core}} || 0 || 0x6 || 0xB || 0xF<hr>''0xE'' || [[Family 6 Model 191]] ?<hr>[[Family 6 Model 190]] ? |
|- | |- | ||
− | | {{intel|Raptor Cove|l=core}} (P) • | + | | {{intel|Raptor Cove|l=core}} (P) • {{intel|Raptor Lake P|RPL-P|l=core}} || 0 || 0x6 || 0xB || 0xA || [[Family 6 Model 186]] |
|- | |- | ||
− | | {{intel|Raptor Cove|l=core}} (P) • | + | | {{intel|Raptor Cove|l=core}} (P) • {{intel|Raptor Lake S|RPL-S|l=core}} <br>Enhanced ''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0xB || 0x7 || [[Family 6 Model 183]] |
|- | |- | ||
! rowspan="2" | {{intel|Alder Lake|l=arch}} ([[2021]]) | ! rowspan="2" | {{intel|Alder Lake|l=arch}} ([[2021]]) | ||
− | | {{intel|Golden Cove|l=arch}} (P) • | + | | {{intel|Golden Cove|l=arch}} (P) • {{intel|Alder Lake P|ADL-P|l=core}} || 0 || 0x6 || 0x9 || 0xA || [[Family 6 Model 154]] |
|- | |- | ||
− | | {{intel|Alder Lake S|l=core}} • ADL-S <br>''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0x9 || 0x7 || [[Family 6 Model 151]] | + | | {{intel|Alder Lake S|l=core}} • {{intel|Alder Lake S|ADL-S|l=core}} <br>''{{intel|Gracemont|l=arch}}'' (E) || 0 || 0x6 || 0x9 || 0x7 || [[Family 6 Model 151]] |
|- | |- | ||
− | | colspan="7" | • ''"Mono" Processors (P-Core)'' • | + | | colspan="7" | • ''"Mono" Processors (P-[[Core]])'' • |
|- | |- | ||
! {{intel|Rocket Lake|l=arch}} ([[2021]]) | ! {{intel|Rocket Lake|l=arch}} ([[2021]]) | ||
− | | {{intel|Cypress Cove|l= | + | | {{intel|Cypress Cove|l=arch}} (P) <br>• {{intel|Rocket Lake S|RKL-S|l=core}}, {{intel|Rocket Lake U|RKL-U|l=core}} || 0 || 0x6 || 0xA || 0x7 || [[Family 6 Model 167]] |
|- <!-- 0xa5: Comet Lake-H/S, 0xa6: Comet Lake-U --> | |- <!-- 0xa5: Comet Lake-H/S, 0xa6: Comet Lake-U --> | ||
! rowspan="2" | {{intel|Comet Lake|l=arch}} ([[2020]]) | ! rowspan="2" | {{intel|Comet Lake|l=arch}} ([[2020]]) | ||
− | | • {{intel|Comet Lake U|U|l=core}} || 0 || 0x6 || 0xA || 0x6 || [[Family 6 Model 166]] ? <!-- 0x8/0xE • 142 ? --> | + | | • {{intel|Comet Lake U|CML-U|l=core}} || 0 || 0x6 || 0xA || 0x6 || [[Family 6 Model 166]] ? <!-- 0x8/0xE • 142 ? --> |
|- | |- | ||
− | | • {{intel|Comet Lake | + | | • {{intel|Comet Lake H|CML-H|l=core}} • {{intel|Comet Lake S|CML-S|l=core}} || 0 || 0x6 || 0xA || 0x5 || [[Family 6 Model 165]] |
|- | |- | ||
! rowspan="2" | {{intel|Tiger Lake|l=arch}} | ! rowspan="2" | {{intel|Tiger Lake|l=arch}} | ||
− | | {{intel|Tiger Lake H|H|l=core}} || 0 || 0x6 || 0x8 || 0xD || [[Family 6 Model 141]] | + | | • {{intel|Tiger Lake H|TGL-H|l=core}} (H35) || 0 || 0x6 || 0x8 || 0xD || [[Family 6 Model 141]] |
|- | |- | ||
− | | {{intel|Tiger Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xC || [[Family 6 Model 140]] | + | | {{intel|Willow Cove|l=arch}} • {{intel|Tiger Lake U|TGL-U|l=core}} (UP) || 0 || 0x6 || 0x8 || 0xC || [[Family 6 Model 140]] |
|- | |- | ||
! rowspan="2" | {{intel|Ice Lake (Client)|l=arch}} | ! rowspan="2" | {{intel|Ice Lake (Client)|l=arch}} | ||
− | | {{intel|Ice Lake U|U|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]] | + | | {{intel|Sunny Cove|l=core}} • {{intel|Ice Lake U|ICL-U|l=core}} || 0 || 0x6 || 0x7 || 0xE || [[Family 6 Model 126]] <!-- H/S/DT --> |
|- | |- | ||
− | | {{intel|Ice Lake Y|Y|l=core}} || 0 || 0x6 || 0x7 || 0xD || [[Family 6 Model 125]] ? | + | | • {{intel|Ice Lake Y|ICL-Y|l=core}} || 0 || 0x6 || 0x7 || 0xD || [[Family 6 Model 125]] ? |
|- | |- | ||
! {{intel|Cannon Lake|l=arch}} | ! {{intel|Cannon Lake|l=arch}} | ||
− | | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 || [[Family 6 Model 102]] | + | | {{intel|Palm Cove|l=arch}} • {{intel|Cannon Lake U|CNL-U|l=core}} (Y) || 0 || 0x6 || 0x6 || 0x6 || [[Family 6 Model 102]] |
|- | |- | ||
! rowspan="2" | {{intel|Coffee Lake|l=arch}} | ! rowspan="2" | {{intel|Coffee Lake|l=arch}} | ||
− | | {{intel|Coffee Lake | + | | • {{intel|Coffee Lake H|CFL-H|l=core}} • {{intel|Coffee Lake S|CFL-S|l=core}} • {{intel|Coffee Lake E|CFL-E|l=core}} || 0 || 0x6 || 0x9 || 0xE || [[Family 6 Model 158]] <!-- (Stepping 10-13) --> |
|- | |- | ||
− | | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]] | + | | • {{intel|Coffee Lake U|CFL-U|l=core}} (R) (Stepping 10) || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]] |
|- <!-- 0x8e: Kaby Lake mobile, 0x9e: Kaby Lake desktop --> | |- <!-- 0x8e: Kaby Lake mobile, 0x9e: Kaby Lake desktop --> | ||
! rowspan="2" | {{intel|Kaby Lake|l=arch}} | ! rowspan="2" | {{intel|Kaby Lake|l=arch}} | ||
− | | {{intel|Kaby Lake DT|DT|l=core}} | + | | • {{intel|Kaby Lake DT|KBL-DT|l=core}} • {{intel|Kaby Lake X|KBL-X|l=core}} <hr>• {{intel|Kaby Lake H|KBL-H|l=core}} • {{intel|Kaby Lake S|KBL-S|l=core}} (G) || 0 || 0x6 || 0x9 || 0xE || [[Family 6 Model 158]] |
|- | |- | ||
− | | {{intel|Kaby Lake Y|Y|l=core}} | + | | • {{intel|Kaby Lake Y|KBL-Y|l=core}} • {{intel|Kaby Lake U|KBL-U|l=core}} (R) || 0 || 0x6 || 0x8 || 0xE || [[Family 6 Model 142]] |
|- | |- | ||
! {{intel|Amber Lake|l=arch}} | ! {{intel|Amber Lake|l=arch}} | ||
− | | {{intel|Amber Lake Y|Y|l=core}} || rowspan="2" | 0 || rowspan="2" | 0x6 || rowspan="2" | 0x8 || rowspan="2" | 0xE || rowspan="2" | [[Family 6 Model 142]] | + | | • {{intel|Amber Lake Y|AML-Y|l=core}} (Stepping 9) || rowspan="2" | 0 || rowspan="2" | 0x6 || rowspan="2" | 0x8 || rowspan="2" | 0xE || rowspan="2" | [[Family 6 Model 142]] |
|- | |- | ||
! {{intel|Whiskey Lake|l=arch}} | ! {{intel|Whiskey Lake|l=arch}} | ||
− | | {{intel|Whiskey Lake U|U|l=core}} | + | | • {{intel|Whiskey Lake U|WHL-U|l=core}} (Stepping 11/12) |
|- <!-- Skylake: 0x4e: Skylake Mobile, 0x5e: Skylake Desktop --> | |- <!-- Skylake: 0x4e: Skylake Mobile, 0x5e: Skylake Desktop --> | ||
! rowspan="2" | {{intel|Skylake (Client)|l=arch}} | ! rowspan="2" | {{intel|Skylake (Client)|l=arch}} | ||
− | | {{intel|Skylake | + | | • {{intel|Skylake H|SKL-H|l=core}} • {{intel|Skylake S|SKL-S|l=core}} • {{intel|Skylake DT|SKL-DT|l=core}} || 0 || 0x6 || 0x5 || 0xE || [[Family 6 Model 94]] |
|- | |- | ||
− | | {{intel|Skylake Y|Y|l=core}} | + | | • {{intel|Skylake Y|SKL-Y|l=core}} • {{intel|Skylake U|SKL-U|l=core}} || 0 || 0x6 || 0x4 || 0xE || [[Family 6 Model 78]] |
|- <!-- Broadwell: Client: 0x3d, 0x47, Server: 0x4f ?, 0x56 ? --> | |- <!-- Broadwell: Client: 0x3d, 0x47, Server: 0x4f ?, 0x56 ? --> | ||
− | ! rowspan=" | + | ! rowspan="2" | {{intel|Broadwell (Client)|l=arch}} |
− | | {{intel|Broadwell C|C|l=core}} | + | | • {{intel|Broadwell H|BDW-H|l=core}} • {{intel|Broadwell C|BDW-C|l=core}} • {{intel|Broadwell W|BDW-W|l=core}} || 0 || 0x6 || 0x4 || 0x7 || [[Family 6 Model 71]] |
|- | |- | ||
− | | {{intel|Broadwell | + | | • {{intel|Broadwell Y|BDW-Y|l=core}} • {{intel|Broadwell U|BDW-U|l=core}} • {{intel|Broadwell S|BDW-S|l=core}} || 0 || 0x6 || 0x3 || 0xD || [[Family 6 Model 61]] |
− | |||
− | |||
|- <!-- Haswell: Client: 0x3c, 0x45, 0x46; Server: 0x3f ? --> | |- <!-- Haswell: Client: 0x3c, 0x45, 0x46; Server: 0x3f ? --> | ||
! rowspan="3" | {{intel|Haswell (Client)|l=arch}} | ! rowspan="3" | {{intel|Haswell (Client)|l=arch}} | ||
− | | {{intel|Haswell | + | | • {{intel|Haswell MB|HSW-MB|l=core}} (GT3E) || 0 || 0x6 || 0x4 || 0x6 || [[Family 6 Model 70]] |
|- | |- | ||
− | | {{intel|Haswell | + | | • {{intel|Haswell U|HSW-U|l=core}} (ULT/ULX/Y) || 0 || 0x6 || 0x4 || 0x5 || [[Family 6 Model 69]] |
|- | |- | ||
− | | {{intel|Haswell S|S|l=core}} || 0 || 0x6 || 0x3 || 0xC || [[Family 6 Model 60]] | + | | • {{intel|Haswell S|HSW-S|l=core}} (H/DT) || 0 || 0x6 || 0x3 || 0xC || [[Family 6 Model 60]] |
|- | |- | ||
! {{intel|Ivy Bridge (Client)|l=arch}} | ! {{intel|Ivy Bridge (Client)|l=arch}} | ||
− | | {{intel|Ivy Bridge M|M|l=core}} | + | | • {{intel|Ivy Bridge M|IVB-M|l=core}} • {{intel|Ivy Bridge H|IVB-H|l=core}} ({{intel|Gladden|l=core}}) || 0 || 0x6 || 0x3 || 0xA || [[Family 6 Model 58]] |
|- | |- | ||
! {{intel|Sandy Bridge (Client)|l=arch}} | ! {{intel|Sandy Bridge (Client)|l=arch}} | ||
− | | {{intel|Sandy Bridge M|M|l=core}} | + | | • {{intel|Sandy Bridge M|SNB-M|l=core}} • {{intel|Sandy Bridge H|SNB-H|l=core}} ({{intel|Celeron|l=celeron}}) || 0 || 0x6 || 0x2 || 0xA || [[Family 6 Model 42]] |
|- | |- | ||
! {{intel|Westmere (Client)|l=arch}} | ! {{intel|Westmere (Client)|l=arch}} | ||
− | | {{intel|Arrandale|l=core}}, | + | | {{intel|Arrandale|l=core}}, {{intel|Clarkdale|l=core}} || 0 || 0x6 || 0x2 || 0x5 || [[Family 6 Model 37]] |
|- | |- | ||
! rowspan="2" | {{intel|Nehalem (Client)|l=arch}} | ! rowspan="2" | {{intel|Nehalem (Client)|l=arch}} | ||
− | | <s>{{intel|Auburndale|l=core}}</s>, | + | | <s>{{intel|Auburndale|l=core}}</s>, <s>{{intel|Havendale|l=core}}</s> || 0 || 0x6 || 0x1 ||0xF || [[Family 6 Model 31]] |
|- | |- | ||
| {{intel|Clarksfield|l=core}} || 0 || 0x6 || 0x1 || 0xE || [[Family 6 Model 30]] | | {{intel|Clarksfield|l=core}} || 0 || 0x6 || 0x1 || 0xE || [[Family 6 Model 30]] | ||
|- | |- | ||
! {{intel|Penryn (Client)|l=arch}} | ! {{intel|Penryn (Client)|l=arch}} | ||
− | | {{intel|Penryn|l= | + | | {{intel|Penryn|l=arch}}, {{intel|Wolfdale|l=core}}, {{intel|Yorkfield|l=core}} || 0 || 0x6 || 0x1 || 0x7 || [[Family 6 Model 23]] |
|- | |- | ||
! rowspan="2" | {{intel|Core (Client)|l=arch}} | ! rowspan="2" | {{intel|Core (Client)|l=arch}} | ||
Line 419: | Line 417: | ||
|- | |- | ||
! rowspan="7" | {{intel|P6|l=arch}} ({{intel|Pentium}}) | ! rowspan="7" | {{intel|P6|l=arch}} ({{intel|Pentium}}) | ||
− | | {{intel|Tualatin|l=core}} || 0 || 0x6 || 0x0 || 0xB || [[Family 6 Model 11]] | + | | {{intel|Tualatin|l=core}} ([[Pentium]] III) || 0 || 0x6 || 0x0 || 0xB || [[Family 6 Model 11]] |
|- | |- | ||
− | | {{intel|Coppermine|l=core}}, | + | | {{intel|Coppermine|l=core}}, {{intel|Coppermine T|l=core}} || 0 || 0x6 || 0x0 || 0x8 || [[Family 6 Model 8]] |
|- | |- | ||
| {{intel|Katmai|l=core}} || 0 || 0x6 || 0x0 || 0x7 || [[Family 6 Model 7]] | | {{intel|Katmai|l=core}} || 0 || 0x6 || 0x0 || 0x7 || [[Family 6 Model 7]] | ||
Line 427: | Line 425: | ||
| || 0 || 0x6 || 0x0 || 0x6 || [[Family 6 Model 6]] | | || 0 || 0x6 || 0x0 || 0x6 || [[Family 6 Model 6]] | ||
|- | |- | ||
− | | || 0 || 0x6 || 0x0 || 0x5 || [[Family 6 Model 5]] | + | | {{intel|Deschutes|l=core}} ([[Pentium]] III) || 0 || 0x6 || 0x0 || 0x5 || [[Family 6 Model 5]] |
|- | |- | ||
− | | || 0 || 0x6 || 0x0 || 0x3 || [[Family 6 Model 3]] | + | | {{intel|Klamath|l=core}} ([[Pentium]] II) || 0 || 0x6 || 0x0 || 0x3 || [[Family 6 Model 3]] |
|- | |- | ||
− | | || 0 || 0x6 || 0x0 || 0x1 || [[Family 6 Model 1]] | + | | [[Pentium]] Pro || 0 || 0x6 || 0x0 || 0x1 || [[Family 6 Model 1]] |
|- | |- | ||
|} | |} | ||
+ | <!-- | ||
+ | #define INTEL_PENTIUM_PRO IFM(6, 0x01) | ||
+ | #define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) | ||
+ | #define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) | ||
+ | #define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B) | ||
+ | #define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D) | ||
+ | |||
+ | #define INTEL_CORE_YONAH IFM(6, 0x0E) | ||
+ | |||
+ | #define INTEL_CORE2_MEROM IFM(6, 0x0F) | ||
+ | #define INTEL_CORE2_MEROM_L IFM(6, 0x16) | ||
+ | #define INTEL_CORE2_PENRYN IFM(6, 0x17) | ||
+ | #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) | ||
+ | |||
+ | #define INTEL_NEHALEM IFM(6, 0x1E) | ||
+ | #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ | ||
+ | #define INTEL_NEHALEM_EP IFM(6, 0x1A) | ||
+ | #define INTEL_NEHALEM_EX IFM(6, 0x2E) | ||
+ | |||
+ | #define INTEL_WESTMERE IFM(6, 0x25) | ||
+ | #define INTEL_WESTMERE_EP IFM(6, 0x2C) | ||
+ | #define INTEL_WESTMERE_EX IFM(6, 0x2F) | ||
+ | |||
+ | #define INTEL_SANDYBRIDGE IFM(6, 0x2A) | ||
+ | #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) | ||
+ | #define INTEL_IVYBRIDGE IFM(6, 0x3A) | ||
+ | #define INTEL_IVYBRIDGE_X IFM(6, 0x3E) | ||
+ | |||
+ | #define INTEL_HASWELL IFM(6, 0x3C) | ||
+ | #define INTEL_HASWELL_X IFM(6, 0x3F) | ||
+ | #define INTEL_HASWELL_L IFM(6, 0x45) | ||
+ | #define INTEL_HASWELL_G IFM(6, 0x46) | ||
+ | |||
+ | #define INTEL_BROADWELL IFM(6, 0x3D) | ||
+ | #define INTEL_BROADWELL_G IFM(6, 0x47) | ||
+ | #define INTEL_BROADWELL_X IFM(6, 0x4F) | ||
+ | #define INTEL_BROADWELL_D IFM(6, 0x56) | ||
+ | |||
+ | #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ | ||
+ | #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ | ||
+ | #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ | ||
+ | /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ | ||
+ | /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ | ||
+ | |||
+ | #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ | ||
+ | /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ | ||
+ | /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ | ||
+ | /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ | ||
+ | |||
+ | #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ | ||
+ | /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ | ||
+ | |||
+ | #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ | ||
+ | #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ | ||
+ | |||
+ | #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ | ||
+ | |||
+ | #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ | ||
+ | #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ | ||
+ | #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ | ||
+ | #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ | ||
+ | #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ | ||
+ | |||
+ | #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ | ||
+ | |||
+ | #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ | ||
+ | #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ | ||
+ | |||
+ | #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ | ||
+ | |||
+ | #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) /* Raptor Cove */ | ||
+ | |||
+ | #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */ | ||
+ | #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) | ||
+ | --> | ||
=== Family 5 === | === Family 5 === |
Latest revision as of 10:40, 9 April 2025
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Calling Convention
- Microarchitectures
- Model-Specific Register
- CPUID
- Assembly
- Interrupts
- Registers
- Micro-Ops
- Timer
CPUIDs
- AMD's CPUIDs
- Intel's CPUIDs
Modes
Extensions(all)
Below is a list of Intel's CPUID broken down by their respective core names and microarchitecture:
Contents
CPUIDs[edit]
Family 19[edit]
Microarchitecture | Core | Platform | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|---|
Diamond Rapids (2025) |
Panther Cove X (P) • 18A DMR-AP/SP (LGA9324) |
Mountain Stream |
0x4 | 0xF | 0x0 | 0x1 | Family 19 Model 1 |
Nova Lake (2026) |
Coyote Cove (P) • 18A Arctic Wolf (E) • NVL-S/H |
0x4 | 0xF | 0x0 | 0x0 | Family 19 Model 0 |
Key changes from Granite Rapids:
- • Core: Redwood Cove+ → Panther Cove X (P-core), Platform: Eagle Stream → Mountain Stream
Family 15[edit]
Microarchitecture | Core | Fab node | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|---|
Modified Pentium M (2006) |
Cedar Mill (2C) (Xeon Dempsey) |
65 nm | 0 | 0xF | 0x0 | 0x6 | Family 15 Model 6 |
Netburst (P68) (2000) |
Prescott (2M) | 90 nm | 0 | 0xF | 0x0 | 0x4 | Family 15 Model 4 |
Prescott | 90 nm | 0 | 0xF | 0x0 | 0x3 | Family 15 Model 3 | |
Northwood | 130 nm | 0 | 0xF | 0x0 | 0x2 | Family 15 Model 2 | |
Willamette (Xeon Foster) |
180 nm | 0 | 0xF | 0x0 | 0x1 | Family 15 Model 1 |
Family 11[edit]
Microarchitecture | Core | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|
Knights Corner (2011) | 62 cores (22 nm) | 0 | 0xB | 0x0 | 0x1 | Family 11 Model 1 |
Knights Ferry (2010) | 32 cores (45 nm) | 0 | 0xB | 0x0 | 0x0 | Family 11 Model 0 |
Family 6[edit]
MIC Architecture[edit]
- • Xeon Phi •
Microarchitecture | Core | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|
Knights Mill |
Xeon Phi 64C/256T 14 nm |
0 | 0x6 | 0x8 | 0x5 | Family 6 Model 133 |
Knights Landing | Xeon Phi 72C/288T 14 nm |
0 | 0x6 | 0x5 | 0x7 | Family 6 Model 87 |
Small Cores[edit]
Intel's client small cores refers to Intel low-power SoCs that ship in low power
- laptops, tablets, embedded devices, and low-power servers.
- • "Small Cores" Processors (Atom/E-Core) •
Microarchitecture | Core | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|
Darkmont (2025) |
Clearwater Forest CWF-AP/CWF-SP Wildcat Lake WCL Panther Lake U/H/P |
0 | 0x6 | 0xD 0x? 0xC |
0xD 0x? 0xC |
Darkmont_X IFM (6, 0xDD) . . |
Skymont (2024) |
Arrow Lake S/U Lunar Lake MX/V |
0 | 0x6 | 0xB 0xB |
0x5 0xC |
0xB 0x5, 0xC 0x5/0x6 0xB 0xC/0xD |
Crestmont (2023) |
Sierra Forest SP Meteor Lake S/N Grand Ridge |
0 | 0x6 | 0xA 0xA 0xB |
0xF 0xA 0x6 |
IFM (6, 0xAF) 0xA, 0xB, 0xC IFM (6, 0xB6) |
Gracemont (2021) |
Alder Lake N Raptor Lake S/N Twin Lake S |
0 | 0x6 | 0xB 0xB 0x? |
0xE 0x7 0x? |
IFM (6, 0xBE) 0xB 0x7/0xB 0xE ? |
Tremont (2020) |
Jasper Lake (L) | 0 | 0x6 | 0x9 | 0xC | Family 6 Model 156 |
Elkhart Lake | 0 | 0x6 | 0x9 | 0x6 | Family 6 Model 150 | |
Jacobsville (D) | 0 | 0x6 | 0x8 | 0x6 | IFM (6, 0x86) | |
Lakefield | 0 | 0x6 | 0x8 | 0xA | Family 6 Model 138 | |
Goldmont Plus | Gemini Lake | 0 | 0x6 | 0x7 | 0xA | Family 6 Model 122 |
Goldmont | Denverton (D) | 0 | 0x6 | 0x5 | 0xF | Family 6 Model 95 |
Apollo Lake, Willow Trail |
0 | 0x6 | 0x5 | 0xC | Family 6 Model 92 | |
Airmont | Cherry Trail, Braswell |
0 | 0x6 | 0x4 | 0xC | Family 6 Model 76 |
Lightning Mountain (NP) |
0 | 0x6 | 0x7 | 0x5 | IFM (6, 0x75) | |
Silvermont | SoFIA | 0 | 0x6 | 0x5 | 0xD | Family 6 Model 93 |
Anniedale (MID2) | 0 | 0x6 | 0x5 | 0xA | Family 6 Model 90 | |
Avoton, Rangeley (D) |
0 | 0x6 | 0x4 | 0xD | Family 6 Model 77 | |
Merriefield, Tangier (MID) |
0 | 0x6 | 0x4 | 0xA | Family 6 Model 74 | |
Bay Trail, Valleyview |
0 | 0x6 | 0x3 | 0x7 | Family 6 Model 55 | |
Saltwell | Cedarview | 0 | 0x6 | 0x3 | 0x6 | Family 6 Model 54 |
Cloverview (TAB) | 0 | 0x6 | 0x3 | 0x5 | Family 6 Model 53 | |
Penwell (MID) | 0 | 0x6 | 0x2 | 0x7 | Family 6 Model 39 | |
Bonnell | Silverthorne, Lincroft (MID) |
0 | 0x6 | 0x2 | 0x6 | Family 6 Model 38 |
Diamondville, Pineview |
0 | 0x6 | 0x1 | 0xC | Family 6 Model 28 |
Big Cores (Server)[edit]
Intel's server big cores refers to Intel workstation and data center SoCs that ship
- in most enterprise desktops, workstations, and servers.
Big Cores (Client)[edit]
Intel's client big cores refers to Intel mainstream SoCs that ship in most tablets, laptops, and desktop devices.
Family 5[edit]
Microarchitecture | Core | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|
Lakemont (Lake) |
Quark D1000 | 0 | 0x5 | 0x0 | 0xA | Family 5 Model 10 |
Quark X1000 | 0 | 0x5 | 0x0 | 0x9 | Family 5 Model 9 | |
P5 (1993) • Pentium |
P55C (Mobile) | 0 | 0x5 | 0x0 | 0x8 | Family 5 Model 8 |
0 | 0x5 | 0x0 | 0x7 | Family 5 Model 7 | ||
P55C (Pentium MMX) | 0 | 0x5 | 0x0 | 0x4 | Family 5 Model 4 | |
P54CS (Pentium 75) | 0 | 0x5 | 0x0 | 0x2 | Family 5 Model 2 | |
P5, P54, P54CQS | 0 | 0x5 | 0x0 | 0x1 | Family 5 Model 1 |
Family 4[edit]
Microarchitecture | Core | Extended Family |
Family | Extended Model |
Model | Family • Model |
---|---|---|---|---|---|---|
Intel 486 (80486) |
0 | 0x4 | 0x0 | 0x9 | Family 4 Model 9 | |
Intel 486DX4 | 0 | 0x4 | 0x0 | 0x8 | Family 4 Model 8 | |
0 | 0x4 | 0x0 | 0x7 | Family 4 Model 7 | ||
0 | 0x4 | 0x0 | 0x5 | Family 4 Model 5 | ||
Intel 486SL | 0 | 0x4 | 0x0 | 0x4 | Family 4 Model 4 | |
Intel 486DX2 | 0 | 0x4 | 0x0 | 0x3 | Family 4 Model 3 | |
Intel 486SX | 0 | 0x4 | 0x0 | 0x2 | Family 4 Model 2 | |
Intel 486DX | 0 | 0x4 | 0x0 | 0x1 | Family 4 Model 1 |