From WikiChip
Difference between revisions of "amd/packages/ft1"
< amd

(Corrected pitch, added more features.)
(Added pin types, chipset interfaces, misc. updates.)
 
Line 4: Line 4:
 
|designer=AMD
 
|designer=AMD
 
|market=Mobile
 
|market=Mobile
 +
|market 2=Embedded
 
|first launched=January 4, 2011
 
|first launched=January 4, 2011
 
|microarch=Bobcat
 
|microarch=Bobcat
 
|tdp=18 W
 
|tdp=18 W
 
|package name=FT1
 
|package name=FT1
−
|package type=Organic Micro Ball Grid Array
+
|package name 2=UOB413
 +
|package type=FC-OBGA
 
|package contacts=413
 
|package contacts=413
 
|package dimension=19.0 mm
 
|package dimension=19.0 mm
 
|package dimension 2=19.0 mm
 
|package dimension 2=19.0 mm
−
|package pitch=0.8-1.0 mm
+
|package dimension 3=1.92 mm
 +
|package pitch=0.8 mm
 
}}
 
}}
 +
'''FT1''' was a CPU package for low power [[AMD]] microprocessors with integrated graphics targeting the thin client, embedded, and tablet market, the successor to the {{\\|ASB2}} package. Its counterparts for the mainstream mobile and desktop markets are {{\\|Socket FS1}} and {{\\|Socket FM1}} respectively. FT1 was superseded by the {{\\|FT3}} package.
  
−
'''FT1''' was a BGA-413 package for low power [[AMD]] microprocessors with integrated graphics targeting the thin client, embedded and tablet market, the successor to the {{\\|ASB2}} package. Its counterparts for the mainstream mobile and desktop markets are {{\\|Socket FS1}} and {{\\|Socket FM1}}, respectively. FT1 was superseded by the {{\\|FT3}} package.
+
Package FT1 was used in AMD's "Brazos" platform for ultrathin notebooks. All processors in the FT1 package are members of AMD's x86 CPU {{amd|CPUID#Family 20 (14h)|Family 14h}} with CPU cores based on the {{amd|Bobcat|l=arch}} microarchitecture, and were manufactured on a [[TSMC]] [[40&nbsp;nm]] bulk CMOS process.
−
 
 
−
Package FT1 was used in AMD's "Brazos" platform for ultrathin notebooks. All processors in the FT1 package are members of AMD's Family 14h with CPU cores based on the {{amd|Bobcat|l=arch}} microarchitecture, and were manufactured on a 40 nm SOI process.
 
−
 
 
  
 
=== Features ===
 
=== Features ===
−
* 413-pin lidless micro ball grid array package, 0.8-1.0 mm multi-pitch, 19 × 19 mm, organic substrate
+
* Lidless [[ball grid array]] package, 19.0&nbsp;mm × 19.0&nbsp;mm × 1.92&nbsp;mm
 +
** 413 contacts, 0.8 - 1.0&nbsp;mm multi-pitch
 +
** Organic substrate, [[flip chip]] die attachment
  
−
* 64 bit DDR3 SDRAM interface up to 667 MHz, PC3-10600 (DDR3-1333), 10.7 GB/s
+
* 1 × 64 bit DDR3 SDRAM interface
−
** Up to 2 UDIMMs or SODIMMs, no ECC support
+
** Up to 667 MHz, PC3-10600 (DDR3-1333), 10.67 GB/s raw bandwidth
 +
** Up to 2 DIMMs
 +
** {{abbr|UDIMM}}, {{abbr|SODIMM}}, or soldered DRAMs
 +
** JEDEC 1.5V, 1.35V
 +
** No ECC support
  
−
* PCIe Gen 1.0 and 2.0 (5 GT/s)
+
* PCIe Gen 1, 2 (5 GT/s) from one 5-port, 8-lane controller
 
** Configurable x4 General Purpose Ports (4x1, 2x2, 1x2 + 2x1, 1x4)
 
** Configurable x4 General Purpose Ports (4x1, 2x2, 1x2 + 2x1, 1x4)
−
** x4 Unified Media Interface to FCH
+
** x4 Unified Media Interface to {{abbr|FCH}}
  
 
* Two independent display controllers
 
* Two independent display controllers
−
** Up to 2 × DisplayPort/eDP 1.1a up to 2560 × 1600 at 60 Hz, 30 bpp
+
** 2 × DisplayPort 1.1a, up to 2560 × 1600 at 60 Hz, 30 bpp
−
** 2 × Single link DVI up to 1920 × 1200 at 60 Hz, 24 bpp
+
** 1 × {{abbr|eDP}} up to 2048 × 1536, 24 bpp, with ext. components
−
** 1 × Single link LVDS up to 1440 × 900 or 1400 × 1050 at 60 Hz, 18 bpp
+
** 1 × {{abbr|LVDS}} up to 1440 × 900 or 1400 × 1050 at 60 Hz, 18 bpp
−
** 1 × HDMI up to 1920 × 1080 at 60 Hz, 36 bpp
+
** 1 × {{abbr|VGA}} up to 2560 × 1600, 400&nbsp;MHz
−
** 1 × VGA/DAC
+
** 2 × {{abbr|SL}} {{abbr|DVI}} up to 1920 × 1200 at 60 Hz, 24 bpp, with ext. components
−
** 1 × DVO
+
** 1 × {{abbr|HDMI}} up to 1920 × 1080 at 60 Hz, 36 bpp, with ext. components
  
 
== Chipsets ==
 
== Chipsets ==
−
* AMD FCH A50M/A55E, codename "Hudson"
+
* AMD {{abbr|FCH}} A50M "Hudson-M1"
 +
* AMD FCH A55E "Hudson-E1"
 +
 
 +
The chipset is attached with an x4 {{abbr|UMI}} link (A50M PCIe Gen 1 (2.5 GT/s), A55E Gen 2) and can provide the following additional interfaces:
 +
* 4 lanes PCIe Gen 1, 2 (5 GT/s) configurable x4/x2/x1
 +
* 32-bit, 33&nbsp;MHz PCI, max. four slots (A55E only)
 +
* 6 × SATA Gen 1, 2, 3 (6 Gb/s)
 +
* 14 × USB 1.1, 2.0
 +
* 2 × USB 1.1
 +
* Gb Ethernet MAC (A55E only)
 +
* {{abbr|HDA}}, {{abbr|LPC}}, {{abbr|SPI}}, {{abbr|SMBus}}, {{abbr|GPIO}}
  
 
== Processors using package FT1 ==
 
== Processors using package FT1 ==
 
<!-- AMD-47534-3.18; CPUID 00500F10h (ON-B0), 00500F20h (ON-C0) -->
 
<!-- AMD-47534-3.18; CPUID 00500F10h (ON-B0), 00500F20h (ON-C0) -->
−
* AMD C-Series codename "Ontario"
+
* AMD C-Series "Ontario" (9&nbsp;W)
−
* AMD E-Series "Zacate"
+
* AMD E-Series "Zacate" (18&nbsp;W)
−
* AMD G-Series
+
* AMD Embedded G-Series "{{amd|eBrazos|l=core}}"
−
* AMD Z-Series "Desna"
+
* AMD Z-Series "Desna" (< 6&nbsp;W)
  
 
<!-- NOTE:
 
<!-- NOTE:
−
          This table is generated automatically from the data in the actual articles.
+
This table is generated automatically from the data in the actual articles.
−
          If a microprocessor is missing from the list, an appropriate article for it needs to be
+
If a microprocessor is missing from the list, an appropriate article for it needs to be
−
          created and tagged accordingly.
+
created and tagged accordingly.
−
 
+
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
−
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
 
-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
−
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19">
+
<table class="comptable sortable">
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of all FT1-based Processors</th></tr>
+
{{comp table header|main|1:&#32;|3:CPU|2:GPU|3:&#32;}}
−
{{comp table header 1|cols=Price, Process, Launched, µarch, Family, Core, C, T, Freq, Turbo, TDP}}
+
{{comp table header|cols|Family|Cores|L2$|Frequ.|Brand|Frequ.|{{abbr|TDP}}|Launched|{{abbr|OPN}}}}
−
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[package::FT1]]
+
{{#ask: [[Category:microprocessor models by amd]] [[package::FT1]]
−
|?full page name
+
|?full page name
−
|?model number
+
|?model number
−
|?release price
+
|?family
−
|?process
+
|?core count
−
|?first launched
+
|?l2$ size#KiB
−
|?microarchitecture
+
|?base frequency#MHz
−
|?microprocessor family
+
|?integrated gpu
−
|?core name
+
|?integrated gpu base frequency#MHz
−
|?core count
+
|?tdp
−
|?thread count
+
|?first launched
−
|?base frequency#GHz
+
|?part number
−
|?turbo frequency (1 core)#GHz
+
|format=template
−
|?tdp
+
|template=proc table 3
−
|format=template
+
|userparam=11
−
|template=proc table 3
+
|mainlabel=-
−
|userparam=13
 
−
|mainlabel=-
 
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[package::FT1]]}}
+
{{comp table count|ask=[[Category:microprocessor models by amd]] [[package::FT1]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
Line 89: Line 103:
 
:[[File:BGA-413 pn.svg|800px]]
 
:[[File:BGA-413 pn.svg|800px]]
  
−
BGA-413 package ball numbers.
+
FT1 package ball numbers.
  
 
== Pin Map ==
 
== Pin Map ==
 
:[[File:BGA-413 pinmap.svg|800px]]
 
:[[File:BGA-413 pinmap.svg|800px]]
 +
 +
FT1 pinout.
 +
<!--
 +
ALERT_L,T2,M_DATA[32],N23,SVC,J1,VDD_18_DAC,W9
 +
CLKIN_H,V2,M_DATA[33],P21,SVD,J2,VDD_33,A4
 +
CLKIN_L,V1,M_DATA[34],T20,TCK,P1,VSS,A7
 +
DAC_BLUE,A13,M_DATA[35],T23,TDI,N2,VSS,B7
 +
DAC_BLUEB,B13,M_DATA[36],M20,TDO,N1,VSS,B11
 +
DAC_GREEN,A12,M_DATA[37],P20,TDP1_AUXN,C2,VSS,B15
 +
DAC_GREENB,B12,M_DATA[38],R23,TDP1_AUXP,B2,VSS,B17
 +
DAC_HSYNC,E1,M_DATA[39],T22,TDP1_HPD,C1,VSS,B22
 +
DAC_RED,C12,M_DATA[40],V20,TDP1_TXN[0],B8,VSS,C4
 +
DAC_REDB,D13,M_DATA[41],V21,TDP1_TXN[1],A9,VSS,D5
 +
DAC_SCL,F2,M_DATA[42],Y23,TDP1_TXN[2],C10,VSS,D7
 +
DAC_SDA,D4,M_DATA[43],Y22,TDP1_TXN[3],B10,VSS,D9
 +
DAC_VSYNC,E2,M_DATA[44],T21,TDP1_TXP[0],A8,VSS,D11
 +
DAC_ZVSS,D12,M_DATA[45],U23,TDP1_TXP[1],B9,VSS,D14
 +
DBRDY,M3,M_DATA[46],W23,TDP1_TXP[2],D10,VSS,D17
 +
DBREQ_L,M1,M_DATA[47],Y21,TDP1_TXP[3],A10,VSS,D19
 +
DISP_CLKIN_H,D2,M_DATA[48],Y20,TEST4,R1,VSS,E7
 +
DISP_CLKIN_L,D1,M_DATA[49],AB22,TEST5,R2,VSS,E9
 +
DMAACTIVE_L,T1,M_DATA[50],AC19,TEST6,R6,VSS,E12
 +
DP_BLON,G2,M_DATA[51],AA18,TEST14,T5,VSS,E20
 +
DP_DIGON,H2,M_DATA[52],AA23,TEST15,E4,VSS,F8
 +
DP_VARY_BL,H1,M_DATA[53],AA20,TEST16,K4,VSS,F11
 +
DP_ZVSS,H3,M_DATA[54],AB19,TEST17,L1,VSS,F13
 +
LTDP0_AUXN,B3,M_DATA[55],Y18,TEST18,L2,VSS,G4
 +
LTDP0_AUXP,A3,M_DATA[56],AC17,TEST19,M2,VSS,G5
 +
LTDP0_HPD,D3,M_DATA[57],Y16,TEST25_H,K1,VSS,G7
 +
LTDP0_TXN[0],A5,M_DATA[58],AB14,TEST25_L,K2,VSS,G9
 +
LTDP0_TXN[1],C6,M_DATA[59],AC14,TEST28_H,L5,VSS,G12
 +
LTDP0_TXN[2],B6,M_DATA[60],AC18,TEST28_L,M5,VSS,G20
 +
LTDP0_TXN[3],C8,M_DATA[61],AB18,TEST31,M21,VSS,G22
 +
LTDP0_TXP[0],B5,M_DATA[62],AB15,TEST33_H,J18,VSS,H6
 +
LTDP0_TXP[1],D6,M_DATA[63],AC15,TEST33_L,J19,VSS,H11
 +
LTDP0_TXP[2],A6,M_DM[0],D15,TEST34_H,U15,VSS,H13
 +
LTDP0_TXP[3],D8,M_DM[1],B19,TEST34_L,T15,VSS,J4
 +
M0_CS_L[0],T17,M_DM[2],D21,TEST35,H4,VSS,J5
 +
M0_CS_L[1],W16,M_DM[3],H22,TEST36,N5,VSS,J7
 +
M0_ODT[0],W19,M_DM[4],P23,TEST37,R5,VSS,J20
 +
M0_ODT[1],V15,M_DM[5],V23,TEST38,K3,VSS,K10
 +
M1_CS_L[0],U17,M_DM[6],AB20,THERMTRIP_L,U2,VSS,K14
 +
M1_CS_L[1],V16,M_DM[7],AA16,TMS,P2,VSS,L4
 +
M1_ODT[0],U19,M_DQS_H[0],A16,TRST_L,M4,VSS,L6
 +
M1_ODT[1],W15,M_DQS_H[1],B20,VDDCR_CPU,E5,VSS,L8
 +
M_ADD[0],R17,M_DQS_H[2],E23,VDDCR_CPU,E6,VSS,L11
 +
M_ADD[1],H19,M_DQS_H[3],J22,VDDCR_CPU,F5,VSS,L13
 +
M_ADD[2],J17,M_DQS_H[4],R22,VDDCR_CPU,F7,VSS,L20
 +
M_ADD[3],H18,M_DQS_H[5],W22,VDDCR_CPU,G6,VSS,L22
 +
M_ADD[4],H17,M_DQS_H[6],AC20,VDDCR_CPU,G8,VSS,M7
 +
M_ADD[5],G17,M_DQS_H[7],AB16,VDDCR_CPU,H5,VSS,N4
 +
M_ADD[6],H15,M_DQS_L[0],B16,VDDCR_CPU,H7,VSS,N6
 +
M_ADD[7],G18,M_DQS_L[1],A20,VDDCR_CPU,J6,VSS,N8
 +
M_ADD[8],F19,M_DQS_L[2],E22,VDDCR_CPU,J8,VSS,N11
 +
M_ADD[9],E19,M_DQS_L[3],J23,VDDCR_CPU,L7,VSS,N13
 +
M_ADD[10],T19,M_DQS_L[4],P22,VDDCR_CPU,M6,VSS,N20
 +
M_ADD[11],F17,M_DQS_L[5],V22,VDDCR_CPU,M8,VSS,N22
 +
M_ADD[12],E18,M_DQS_L[6],AC21,VDDCR_CPU,N7,VSS,P10
 +
M_ADD[13],W17,M_DQS_L[7],AC16,VDDCR_CPU,R8,VSS,P14
 +
M_ADD[14],E16,M_EVENT_L,N17,VDDCR_CPU_SENSE,G1,VSS,R4
 +
M_ADD[15],G15,M_RAS_L,U18,VDDCR_NB,E8,VSS,R7
 +
M_BANK[0],R18,M_RESET_L,L23,VDDCR_NB,E11,VSS,R20
 +
M_BANK[1],T18,M_VREF,M23,VDDCR_NB,E13,VSS,T6
 +
M_BANK[2],F16,M_WE_L,V17,VDDCR_NB,F9,VSS,T9
 +
M_CAS_L,V19,M_ZVDDIO_MEM_S,M22,VDDCR_NB,F12,VSS,T11
 +
M_CKE[0],F15,PROCHOT_L,U1,VDDCR_NB,G11,VSS,T13
 +
M_CKE[1],E15,PWROK,T4,VDDCR_NB,G13,VSS,U4
 +
M_CLK_H[0],M17,P_GPP_RXN[0],Y6,VDDCR_NB,H9,VSS,U5
 +
M_CLK_H[1],M19,P_GPP_RXN[1],AC4,VDDCR_NB,H12,VSS,U7
 +
M_CLK_H[2],N18,P_GPP_RXN[2],AA2,VDDCR_NB,K11,VSS,U12
 +
M_CLK_H[3],L18,P_GPP_RXN[3],Y3,VDDCR_NB,K13,VSS,U20
 +
M_CLK_L[0],M16,P_GPP_RXP[0],AA6,VDDCR_NB,L10,VSS,U22
 +
M_CLK_L[1],M18,P_GPP_RXP[1],AB4,VDDCR_NB,L12,VSS,V8
 +
M_CLK_L[2],N19,P_GPP_RXP[2],AA1,VDDCR_NB,L14,VSS,V9
 +
M_CLK_L[3],L17,P_GPP_RXP[3],Y4,VDDCR_NB,M11,VSS,V11
 +
M_DATA[0],B14,P_GPP_TXN[0],AC6,VDDCR_NB,M12,VSS,V13
 +
M_DATA[1],A15,P_GPP_TXN[1],AC3,VDDCR_NB,M13,VSS,W1
 +
M_DATA[2],A17,P_GPP_TXN[2],Y2,VDDCR_NB,N10,VSS,W2
 +
M_DATA[3],D18,P_GPP_TXN[3],V4,VDDCR_NB,N12,VSS,W4
 +
M_DATA[4],A14,P_GPP_TXP[0],AB6,VDDCR_NB,N14,VSS,W5
 +
M_DATA[5],C14,P_GPP_TXP[1],AB3,VDDCR_NB,P11,VSS,W7
 +
M_DATA[6],C16,P_GPP_TXP[2],Y1,VDDCR_NB,P13,VSS,W12
 +
M_DATA[7],D16,P_GPP_TXP[3],V3,VDDCR_NB_SENSE,F4,VSS,W20
 +
M_DATA[8],C18,P_UMI_RXN[0],Y12,VDDIO_MEM_S,E17,VSS,Y5
 +
M_DATA[9],A19,P_UMI_RXN[1],Y10,VDDIO_MEM_S,G16,VSS,Y7
 +
M_DATA[10],B21,P_UMI_RXN[2],AC10,VDDIO_MEM_S,G19,VSS,Y9
 +
M_DATA[11],D20,P_UMI_RXN[3],AB7,VDDIO_MEM_S,J16,VSS,Y11
 +
M_DATA[12],A18,P_UMI_RXP[0],AA12,VDDIO_MEM_S,L16,VSS,Y13
 +
M_DATA[13],B18,P_UMI_RXP[1],AA10,VDDIO_MEM_S,L19,VSS,Y15
 +
M_DATA[14],A21,P_UMI_RXP[2],AB10,VDDIO_MEM_S,N16,VSS,Y17
 +
M_DATA[15],C20,P_UMI_RXP[3],AC7,VDDIO_MEM_S,R16,VSS,Y19
 +
M_DATA[16],C23,P_UMI_TXN[0],AC12,VDDIO_MEM_S,R19,VSS,AA4
 +
M_DATA[17],D23,P_UMI_TXN[1],AB11,VDDIO_MEM_S,U16,VSS,AA22
 +
M_DATA[18],F23,P_UMI_TXN[2],Y8,VDDIO_MEM_S,W18,VSS,AB2
 +
M_DATA[19],F22,P_UMI_TXN[3],AC8,VDDIO_MEM_S_SENSE,F3,VSS,AB5
 +
M_DATA[20],C22,P_UMI_TXP[0],AB12,VDDPL_10,U11,VSS,AB9
 +
M_DATA[21],D22,P_UMI_TXP[1],AC11,VDD_10,T12,VSS,AB13
 +
M_DATA[22],F20,P_UMI_TXP[2],AA8,VDD_10,U13,VSS,AB17
 +
M_DATA[23],F21,P_UMI_TXP[3],AB8,VDD_10,V12,VSS,AB21
 +
M_DATA[24],H21,P_ZVDD_10,Y14,VDD_10,W13,VSS,AC5
 +
M_DATA[25],H23,P_ZVSS,AA14,VDD_18,T7,VSS,AC9
 +
M_DATA[26],K22,RESET_L,T3,VDD_18,U6,VSS,AC13
 +
M_DATA[27],K21,RSVD,B4,VDD_18,U8,VSSBG_DAC,A11
 +
M_DATA[28],G23,RSVD,V5,VDD_18,U9,VSS_SENSE,F1
 +
M_DATA[29],H20,RSVD,W11,VDD_18,V7
 +
M_DATA[30],K20,SIC,P3,VDD_18,W6
 +
M_DATA[31],K23,SID,P4,VDD_18,W8
 +
-->
  
 
=== Pin Description ===
 
=== Pin Description ===
−
{| class="wikitable"
+
{| class="wikitable sortable"
−
!Signal!!Description
+
!Signal!!Type!!Description
 +
|-
 +
|M_ADD[15:0]||O-IO-S||DRAM Column/Row Address
 +
|-
 +
|M_BANK[2:0]||O-IO-S||DRAM Bank Address
 +
|-
 +
|M_CAS_L||O-IO-S||DRAM Column Address Strobe
 +
|-
 +
|M_CKE[1:0]||O-IO-S||DRAM Clock Enable
 +
|-
 +
|M_CLK_H/L[3:0]||O-IO-S||DRAM Differential Clock
 +
|-
 +
|M_DATA[63:0]||B-IO-S||DRAM Data Bus
 +
|-
 +
|M_DM[7:0]||O-IO-S||DRAM Data Mask
 +
|-
 +
|M_DQS_H/L[7:0]||B-IO-D||DRAM Differential Data Strobe
 +
|-
 +
|M_EVENT_L||I-IO-S||DRAM Thermal Event
 +
|-
 +
|M_RAS_L||O-IO-S||DRAM Row Address Strobe
 +
|-
 +
|M_RESET_L||O-IO-S||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
 +
|-
 +
|M_VREF||VREF||Memory Interface Voltage Reference
 +
|-
 +
|M_WE_L||O-IO-S||DRAM Write Enable
 +
|-
 +
|M0_CS_L[1:0], M1_CS_L[1:0]||O-IO-S||DRAM Chip Selects
 +
|-
 +
|M0_ODT[1:0], M1_ODT[1:0]||O-IO-S||DRAM Enable Pin for On Die Termination
 +
|-
 +
|M_ZVDDIO_MEM_S||A||DRAM Interface Drive-Strength Compensation Resistor to VDDIO
 
|-
 
|-
−
|ALERT_L||Programmable pin that can indicate different events, including a SB-TSI interrupt
+
|P_GPP_RXP/RXN[3:0]||I-PCIe-D||General Purpose External PCIe Receive Data Differential Pairs
 
|-
 
|-
−
|CLKIN_H/L||100 MHz PLL Differential Reference Clock
+
|P_GPP_TXP/TXN[3:0]||O-PCIe-D||General Purpose External PCIe Transmit Data Differential Pairs
 
|-
 
|-
−
|DAC_BLUE, DAC_BLUEB||Blue for Video Monitor Output
+
|P_UMI_RXP/RXN[3:0]||I-PCIe-D||Unified Media Interface Receive Data Differential Pairs
 
|-
 
|-
−
|DAC_GREEN, DAC_GREENB||Green for Video Monitor Output
+
|P_UMI_TXP/TXN[3:0]||O-PCIe-D||Unified Media Interface Transmit Data Differential Pairs
 
|-
 
|-
−
|DAC_HSYNC, DAC_VSYNC||Display Horizontal, Vertical Sync
+
|P_ZVDD_10||A||PCIe Drive-Strength Compensation Resistor to P_VDD_10 Power Supply
 
|-
 
|-
−
|DAC_RED, DAC_REDB||Red for Video Monitor Output
+
|P_ZVSS||A||PCIe Drive-Strength Compensation Resistor to VSS
 
|-
 
|-
−
|DAC_SCL, DAC_SDA||I2C Clock, Data for Display (to video monitor)
+
|LTDP0_TXP/TXN[3:0]||O-PCIe-D||{{abbr|LVDS}}/{{abbr|TMDS}} DisplayPort 0 Differential Transmitter
 
|-
 
|-
−
|DAC_ZVSS||Compensation Resistor to DAC Ground Pin
+
|TDP1_TXP/TXN[3:0]||O-PCIe-D||TMDS DisplayPort 1 Differential Transmitter
 
|-
 
|-
−
|DBREQ_L/DBRDY||Debug Request/Ready
+
|LTDP0/TDP1_AUXP/AUXN||B-IO33-D||DisplayPort Auxiliary Channel
 
|-
 
|-
−
|DISP_CLKIN_H/L||100 MHz Display Controller Reference Clock
+
|LTDP0/TDP1_HPD||I-IO33-S||DisplayPort Hot Plug Detect
 
|-
 
|-
−
|DMAACTIVE_L||Indicated System DMA Activity
+
|DP_BLON||O-IO33-S||Display Panel Backlight Enable
 
|-
 
|-
−
|DP_BLON||Display Panel Backlight Enable
+
|DP_DIGON||O-IO33-S||Display Panel Power Enable
 
|-
 
|-
−
|DP_DIGON||Display Panel Power Enable
+
|DP_VARY_BL||O-IO33-S||Display Backlight Brightness Control
 
|-
 
|-
−
|DP_VARY_BL||Display Backlight Brightness Control
+
|DP_ZVSS||A||DP Drive-Strength Compensation Resistor to VSS
 
|-
 
|-
−
|DP_ZVSS||Compensation Resistor to VSS
+
|DAC_RED, DAC_REDB||A||Red for Video Monitor Output
 
|-
 
|-
−
|LTDP0/TDP1_AUXP/N||DisplayPort Auxiliary Channel
+
|DAC_GREEN, DAC_GREENB||A||Green for Video Monitor Output
 
|-
 
|-
−
|LTDP0/TDP1_HPD||DisplayPort Hot Plug Detect
+
|DAC_BLUE, DAC_BLUEB||A||Blue for Video Monitor Output
 
|-
 
|-
−
|LTDP0/TDP1_TXP/N[3:0]||DisplayPort Differential Transmitter
+
|DAC_HSYNC, DAC_VSYNC||O-IO33-S||Display Horizontal, Vertical Sync
 
|-
 
|-
−
|M0_CS_L[1:0], M1_CS_L[1:0]||DRAM Chip Selects
+
|DAC_SCL||O-IO33-OD||{{abbr|I<sup>2</sup>C}} Clock for Display (to video monitor)
 
|-
 
|-
−
|M0_ODT[1:0], M1_ODT[1:0]||DRAM Enable Pin for On Die Termination
+
|DAC_SDA||B-IO33-OD||I<sup>2</sup>C Data for Display
 
|-
 
|-
−
|M_ADD[15:0]||DRAM Column/Row Address
+
|DAC_ZVSS||A||DAC Drive-Strength Compensation Resistor to DAC Ground Pin
 
|-
 
|-
−
|M_BANK[2:0]||DRAM Bank Address
+
|CLKIN_H/L||I-IO18-D||100&nbsp;MHz PLL Differential Reference Clock
 
|-
 
|-
−
|M_CAS_L||DRAM Column Address Strobe
+
|DISP_CLKIN_H/L||I-IO18-D||100&nbsp;MHz Display Controller Reference Clock
 
|-
 
|-
−
|M_CKE[1:0]||DRAM Clock Enable
+
|DMAACTIVE_L||I-IO18-S||Indicated System DMA Activity
 
|-
 
|-
−
|M_CLK_H/L[3:0]||DRAM Differential Clock
+
|PWROK||I-IO18-S||Voltages and CLKIN have reached specified operation
 
|-
 
|-
−
|M_DATA[63:0]||DRAM Interface Data Bus
+
|RESET_L||I-IO18-S||Processor Reset
 
|-
 
|-
−
|M_DM[7:0]||DRAM Data Mask
+
|ALERT_L||O-IO33-OD||Programmable pin that can indicate different events, including a {{abbr|SB-TSI}} interrupt
 
|-
 
|-
−
|M_DQS_H/L[7:0]||DRAM Differential Data Strobe
+
|PROCHOT_L||B-IO33-OD||Processor in {{x86|Hardware Thermal Control|HTC}}-active state
 
|-
 
|-
−
|M_EVENT_L||DRAM Thermal Event
+
|SIC||I-IO33-S||Sideband Interface ({{abbr|SB-TSI}}) Clock
 
|-
 
|-
−
|M_RAS_L||DRAM Row Address Strobe
+
|SID||B-IO33-OD||Sideband Interface Data
 
|-
 
|-
−
|M_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
+
|THERMTRIP_L||O-IO33-OD||{{x86|Thermal protection|Thermal Sensor Trip}} Output
 
|-
 
|-
−
|M_VREF||Memory Interface Voltage Reference
+
|DBREQ_L||I-IO18-S||Debug Request
 
|-
 
|-
−
|M_WE_L||DRAM Write Enable
+
|DBRDY||O-IO18-S||Debug Ready
 
|-
 
|-
−
|M_ZVDDIO_MEM_S||Compensation Resistor to VDDIO
+
|TCK||I-IO18-S||{{abbr|JTAG}} Clock
 
|-
 
|-
−
|PROCHOT_L||Processor in HTC-active state input/output
+
|TDI||I-IO18-S||JTAG Data Input
 
|-
 
|-
−
|PWROK||Voltages and CLKIN have reached specified operation
+
|TDO||O-IO18-S||JTAG Data Output
 
|-
 
|-
−
|P_GPP_TX/RXP/N[3:0]||General Purpose External PCIe Transmit/Receive Data Differential Pairs
+
|TMS||I-IO18-S||JTAG Mode Select
 
|-
 
|-
−
|P_UMI_TX/RXP/N[3:0]||Unified Media Interface Transmit/Receive Data Differential Pairs
+
|TRST_L||I-IO18-S||JTAG Reset
 
|-
 
|-
−
|P_ZVDD_10||Compensation Resistor to P_VDD_10 Power Supply
+
|TEST*||||Test signal
 
|-
 
|-
−
|P_ZVSS||Compensation Resistor to VSS
+
|SVC||O-IO18-S||Serial VID Interface Clock
 
|-
 
|-
−
|RESET_L||Processor Reset
+
|SVD||B-IO18-OD||Serial VID Interface Data
 
|-
 
|-
−
|RSVD||Reserved
+
|VDDCR_CPU||S||Core Power Supply
 
|-
 
|-
−
|SIC, SID||Sideband Temperature Sensor Interface Clock, Data
+
|VDDCR_CPU_SENSE||A||VDDCR_CPU Voltage Monitor Pin
 
|-
 
|-
−
|SVC, SVD||Serial VID Interface Clock, Data
+
|VDDCR_NB||S||Northbridge Power Supply
 
|-
 
|-
−
|TCK, TDI, TDO, TMS, TRST_L||JTAG interface
+
|VDDCR_NB_SENSE||A||VDDCR_NB Voltage Monitor Pin
 
|-
 
|-
−
|TEST*||Test signal
+
|VDDIO_MEM_S||S||DRAM I/O Ring Power Supply
 
|-
 
|-
−
|THERMTRIP_L||Thermal Sensor Trip output
+
|VDDIO_MEM_S_SENSE||A||VDDIO_MEM_S Voltage Monitor Pin
 
|-
 
|-
−
|VDDCR_CPU_SENSE||VDDCR_CPU Voltage Monitor Pin
+
|VDD_10||S||1.05&nbsp;V Supply Pins
 
|-
 
|-
−
|VDDCR_CPU||Core Power Supply
+
|VDDPL_10||S||1.05&nbsp;V Supply Pin for System PLL
 
|-
 
|-
−
|VDDCR_NB_SENSE||VDDCR_NB Voltage Monitor Pin
+
|VDD_18||S||1.8&nbsp;V Supply Pins
 
|-
 
|-
−
|VDDCR_NB||Northbridge Power Supply
+
|VDD_18_DAC||S||1.8&nbsp;V Supply Pin for DAC
 
|-
 
|-
−
|VDDIO_MEM_S_SENSE||VDDIO_MEM_S Voltage Monitor Pin
+
|VDD_33||S||3.3&nbsp;V Supply Pin
 
|-
 
|-
−
|VDDIO_MEM_S||DDR SDRAM I/O Ring Power Supply
+
|VSS||S||Ground
 
|-
 
|-
−
|VDDPL_10||1.05 V Supply Pin for System PLL
+
|VSS_SENSE||A||VSS Voltage Monitor Pin
 
|-
 
|-
−
|VDD_10||1.05 V Supply Pins
+
|VSSBG_DAC||S||DAC Ground
 
|-
 
|-
−
|VDD_18_DAC||1.8 V Supply Pin for DAC
+
|RSVD||||Reserved
 +
|}
 +
 
 +
==== Pin Types ====
 +
{| class="wikitable"
 +
|I/O-PCIe-D||Input / Output, PCIe Voltage Domain, Differential
 
|-
 
|-
−
|VDD_18||1.8 V Supply Pins
+
|I/O/B-IO-D/S/OD||Input / Output / Bidirectional, VDDIO_MEM_S, Differential / Single-Ended / Open Drain
 
|-
 
|-
−
|VDD_33||3.3 V Supply Pin
+
|I/O/B-IO18-D/S/OD||Input / Output / Bidirectional, VDD_18, Differential / Single-Ended / Open Drain
 
|-
 
|-
−
|VSSBG_DAC||DAC Ground
+
|I/O/B-IO33-D/S/OD||Input / Output / Bidirectional, VDD_33, Differential / Single-Ended / Open Drain
 
|-
 
|-
−
|VSS_SENSE||VSS Voltage Monitor Pin
+
|A||Analog
 
|-
 
|-
−
|VSS||Ground
+
|S||Supply Voltage
 
|}
 
|}
  
−
== References ==
+
== Bibliography ==
−
* "FT1 Processor Functional Data Sheet", AMD Publ. #44444, Rev. 2.05, November 2010
+
* {{cite techdoc|title=FT1 Processor Functional Data Sheet|publ=AMD|pid=44444|rev=2.05|date=2010-11}}
−
* "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #43170, Rev. 3.13, February 17, 2012
+
* {{cite techdoc|title=BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors|url=https://www.amd.com/system/files/TechDocs/43170_14h_Mod_00h-0Fh_BKDG.pdf|publ=AMD|pid=43170|rev=3.13|date=2012-02-17}}
−
* "Revision Guide for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #47534, Rev. 3.18, February 26, 2013
+
* {{cite techdoc|title=Revision Guide for AMD Family 14h Models 00h-0Fh Processors|url=https://www.amd.com/system/files/TechDocs/47534_14h_Mod_00h-0Fh_Rev_Guide.pdf|publ=AMD|pid=47534|rev=3.18|date=2013-02-26}}
  
 
== See also ==
 
== See also ==

Latest revision as of 23:31, 3 April 2022

Edit Values
FT1
General Info
DesignerAMD
IntroductionJanuary 4, 2011 (launched)
MarketMobile, Embedded
MicroarchitectureBobcat
TDP18 W
18,000 mW
0.0241 hp
0.018 kW
Package
NameFT1,
UOB413
TypeFC-OBGA
Contacts413
Dimension19.0 mm
1.9 cm
0.748 in
× 19.0 mm
1.9 cm
0.748 in
× 1.92 mm
0.0756 in
Pitch0.8 mm
0.0315 in

FT1 was a CPU package for low power AMD microprocessors with integrated graphics targeting the thin client, embedded, and tablet market, the successor to the ASB2 package. Its counterparts for the mainstream mobile and desktop markets are Socket FS1 and Socket FM1 respectively. FT1 was superseded by the FT3 package.

Package FT1 was used in AMD's "Brazos" platform for ultrathin notebooks. All processors in the FT1 package are members of AMD's x86 CPU Family 14h with CPU cores based on the Bobcat microarchitecture, and were manufactured on a TSMC 40 nm bulk CMOS process.

Features[edit]

  • Lidless ball grid array package, 19.0 mm × 19.0 mm × 1.92 mm
    • 413 contacts, 0.8 - 1.0 mm multi-pitch
    • Organic substrate, flip chip die attachment
  • 1 × 64 bit DDR3 SDRAM interface
    • Up to 667 MHz, PC3-10600 (DDR3-1333), 10.67 GB/s raw bandwidth
    • Up to 2 DIMMs
    • UDIMM, SODIMM, or soldered DRAMs
    • JEDEC 1.5V, 1.35V
    • No ECC support
  • PCIe Gen 1, 2 (5 GT/s) from one 5-port, 8-lane controller
    • Configurable x4 General Purpose Ports (4x1, 2x2, 1x2 + 2x1, 1x4)
    • x4 Unified Media Interface to FCH
  • Two independent display controllers
    • 2 × DisplayPort 1.1a, up to 2560 × 1600 at 60 Hz, 30 bpp
    • 1 × eDP up to 2048 × 1536, 24 bpp, with ext. components
    • 1 × LVDS up to 1440 × 900 or 1400 × 1050 at 60 Hz, 18 bpp
    • 1 × VGA up to 2560 × 1600, 400 MHz
    • 2 × SL DVI up to 1920 × 1200 at 60 Hz, 24 bpp, with ext. components
    • 1 × HDMI up to 1920 × 1080 at 60 Hz, 36 bpp, with ext. components

Chipsets[edit]

  • AMD FCH A50M "Hudson-M1"
  • AMD FCH A55E "Hudson-E1"

The chipset is attached with an x4 UMI link (A50M PCIe Gen 1 (2.5 GT/s), A55E Gen 2) and can provide the following additional interfaces:

  • 4 lanes PCIe Gen 1, 2 (5 GT/s) configurable x4/x2/x1
  • 32-bit, 33 MHz PCI, max. four slots (A55E only)
  • 6 × SATA Gen 1, 2, 3 (6 Gb/s)
  • 14 × USB 1.1, 2.0
  • 2 × USB 1.1
  • Gb Ethernet MAC (A55E only)
  • HDA, LPC, SPI, SMBus, GPIO

Processors using package FT1[edit]

  • AMD C-Series "Ontario" (9 W)
  • AMD E-Series "Zacate" (18 W)
  • AMD Embedded G-Series "eBrazos"
  • AMD Z-Series "Desna" (< 6 W)
  CPUGPU
ModelFamilyCoresL2$Frequ.BrandFrequ.TDPLaunchedOPN
T16REmbedded G-Series1512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
615 MHz
0.615 GHz
615,000 kHz
Radeon HD 6250276 MHz
0.276 GHz
276,000 KHz
4.5 W
4,500 mW
0.00603 hp
0.0045 kW
June 2012GET16RFWB12GVE
T24LEmbedded G-Series1512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
1,000 MHz
1 GHz
1,000,000 kHz
5 W
5,000 mW
0.00671 hp
0.005 kW
1 March 2011GET24LFQB12GVE
T30LEmbedded G-Series1512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
1,400 MHz
1.4 GHz
1,400,000 kHz
18 W
18,000 mW
0.0241 hp
0.018 kW
1 March 2011GET30LGBB12GVE
T40EEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,000 MHz
1 GHz
1,000,000 kHz
Radeon HD 6250280 MHz
0.28 GHz
280,000 KHz
6.4 W
6,400 mW
0.00858 hp
0.0064 kW
23 May 2011GET40EFSB22GVE
T40NEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,000 MHz
1 GHz
1,000,000 kHz
Radeon HD 6290280 MHz
0.28 GHz
280,000 KHz
18 W
18,000 mW
0.0241 hp
0.018 kW
19 January 2011GET40NFPB22GVE
T40REmbedded G-Series1512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
1,000 MHz
1 GHz
1,000,000 kHz
Radeon HD 6250280 MHz
0.28 GHz
280,000 KHz
5.5 W
5,500 mW
0.00738 hp
0.0055 kW
23 May 2011GET40RFSB12GVE
T44REmbedded G-Series1512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
1,200 MHz
1.2 GHz
1,200,000 kHz
Radeon HD 6250280 MHz
0.28 GHz
280,000 KHz
9 W
9,000 mW
0.0121 hp
0.009 kW
19 January 2011GET44RFPB12GVE
T48EEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,400 MHz
1.4 GHz
1,400,000 kHz
Radeon HD 6250280 MHz
0.28 GHz
280,000 KHz
18 W
18,000 mW
0.0241 hp
0.018 kW
2012GET48EGBB22GVE
T48LEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,400 MHz
1.4 GHz
1,400,000 kHz
18 W
18,000 mW
0.0241 hp
0.018 kW
1 March 2011GET48LGBB22GVE
T48NEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,400 MHz
1.4 GHz
1,400,000 kHz
Radeon HD 6310520 MHz
0.52 GHz
520,000 KHz
18 W
18,000 mW
0.0241 hp
0.018 kW
19 January 2011GET48NGBB22GVE
T52REmbedded G-Series1512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
1,500 MHz
1.5 GHz
1,500,000 kHz
Radeon HD 6310500 MHz
0.5 GHz
500,000 KHz
18 W
18,000 mW
0.0241 hp
0.018 kW
19 January 2011GET52RGBB12GVE
T56EEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,650 MHz
1.65 GHz
1,650,000 kHz
Radeon HD 6250275 MHz
0.275 GHz
275,000 KHz
18 W
18,000 mW
0.0241 hp
0.018 kW
2012GET56EGBB22GVE
T56NEmbedded G-Series21,024 KiB
1 MiB
1,048,576 B
9.765625e-4 GiB
1,650 MHz
1.65 GHz
1,650,000 kHz
Radeon HD 6320500 MHz
0.5 GHz
500,000 KHz
18 W
18,000 mW
0.0241 hp
0.018 kW
19 January 2011GET56NGBB22GVE
Count: 13

Package Diagram[edit]

BGA-413 diag.svg

All dimensions in millimeters.

BGA-413 pn.svg

FT1 package ball numbers.

Pin Map[edit]

BGA-413 pinmap.svg

FT1 pinout.

Pin Description[edit]

Signal Type Description
M_ADD[15:0] O-IO-S DRAM Column/Row Address
M_BANK[2:0] O-IO-S DRAM Bank Address
M_CAS_L O-IO-S DRAM Column Address Strobe
M_CKE[1:0] O-IO-S DRAM Clock Enable
M_CLK_H/L[3:0] O-IO-S DRAM Differential Clock
M_DATA[63:0] B-IO-S DRAM Data Bus
M_DM[7:0] O-IO-S DRAM Data Mask
M_DQS_H/L[7:0] B-IO-D DRAM Differential Data Strobe
M_EVENT_L I-IO-S DRAM Thermal Event
M_RAS_L O-IO-S DRAM Row Address Strobe
M_RESET_L O-IO-S DRAM Reset Pin for Suspend-to-RAM Power Management Mode
M_VREF VREF Memory Interface Voltage Reference
M_WE_L O-IO-S DRAM Write Enable
M0_CS_L[1:0], M1_CS_L[1:0] O-IO-S DRAM Chip Selects
M0_ODT[1:0], M1_ODT[1:0] O-IO-S DRAM Enable Pin for On Die Termination
M_ZVDDIO_MEM_S A DRAM Interface Drive-Strength Compensation Resistor to VDDIO
P_GPP_RXP/RXN[3:0] I-PCIe-D General Purpose External PCIe Receive Data Differential Pairs
P_GPP_TXP/TXN[3:0] O-PCIe-D General Purpose External PCIe Transmit Data Differential Pairs
P_UMI_RXP/RXN[3:0] I-PCIe-D Unified Media Interface Receive Data Differential Pairs
P_UMI_TXP/TXN[3:0] O-PCIe-D Unified Media Interface Transmit Data Differential Pairs
P_ZVDD_10 A PCIe Drive-Strength Compensation Resistor to P_VDD_10 Power Supply
P_ZVSS A PCIe Drive-Strength Compensation Resistor to VSS
LTDP0_TXP/TXN[3:0] O-PCIe-D LVDS/TMDS DisplayPort 0 Differential Transmitter
TDP1_TXP/TXN[3:0] O-PCIe-D TMDS DisplayPort 1 Differential Transmitter
LTDP0/TDP1_AUXP/AUXN B-IO33-D DisplayPort Auxiliary Channel
LTDP0/TDP1_HPD I-IO33-S DisplayPort Hot Plug Detect
DP_BLON O-IO33-S Display Panel Backlight Enable
DP_DIGON O-IO33-S Display Panel Power Enable
DP_VARY_BL O-IO33-S Display Backlight Brightness Control
DP_ZVSS A DP Drive-Strength Compensation Resistor to VSS
DAC_RED, DAC_REDB A Red for Video Monitor Output
DAC_GREEN, DAC_GREENB A Green for Video Monitor Output
DAC_BLUE, DAC_BLUEB A Blue for Video Monitor Output
DAC_HSYNC, DAC_VSYNC O-IO33-S Display Horizontal, Vertical Sync
DAC_SCL O-IO33-OD I2C Clock for Display (to video monitor)
DAC_SDA B-IO33-OD I2C Data for Display
DAC_ZVSS A DAC Drive-Strength Compensation Resistor to DAC Ground Pin
CLKIN_H/L I-IO18-D 100 MHz PLL Differential Reference Clock
DISP_CLKIN_H/L I-IO18-D 100 MHz Display Controller Reference Clock
DMAACTIVE_L I-IO18-S Indicated System DMA Activity
PWROK I-IO18-S Voltages and CLKIN have reached specified operation
RESET_L I-IO18-S Processor Reset
ALERT_L O-IO33-OD Programmable pin that can indicate different events, including a SB-TSI interrupt
PROCHOT_L B-IO33-OD Processor in HTC-active state
SIC I-IO33-S Sideband Interface (SB-TSI) Clock
SID B-IO33-OD Sideband Interface Data
THERMTRIP_L O-IO33-OD Thermal Sensor Trip Output
DBREQ_L I-IO18-S Debug Request
DBRDY O-IO18-S Debug Ready
TCK I-IO18-S JTAG Clock
TDI I-IO18-S JTAG Data Input
TDO O-IO18-S JTAG Data Output
TMS I-IO18-S JTAG Mode Select
TRST_L I-IO18-S JTAG Reset
TEST* Test signal
SVC O-IO18-S Serial VID Interface Clock
SVD B-IO18-OD Serial VID Interface Data
VDDCR_CPU S Core Power Supply
VDDCR_CPU_SENSE A VDDCR_CPU Voltage Monitor Pin
VDDCR_NB S Northbridge Power Supply
VDDCR_NB_SENSE A VDDCR_NB Voltage Monitor Pin
VDDIO_MEM_S S DRAM I/O Ring Power Supply
VDDIO_MEM_S_SENSE A VDDIO_MEM_S Voltage Monitor Pin
VDD_10 S 1.05 V Supply Pins
VDDPL_10 S 1.05 V Supply Pin for System PLL
VDD_18 S 1.8 V Supply Pins
VDD_18_DAC S 1.8 V Supply Pin for DAC
VDD_33 S 3.3 V Supply Pin
VSS S Ground
VSS_SENSE A VSS Voltage Monitor Pin
VSSBG_DAC S DAC Ground
RSVD Reserved

Pin Types[edit]

I/O-PCIe-D Input / Output, PCIe Voltage Domain, Differential
I/O/B-IO-D/S/OD Input / Output / Bidirectional, VDDIO_MEM_S, Differential / Single-Ended / Open Drain
I/O/B-IO18-D/S/OD Input / Output / Bidirectional, VDD_18, Differential / Single-Ended / Open Drain
I/O/B-IO33-D/S/OD Input / Output / Bidirectional, VDD_33, Differential / Single-Ended / Open Drain
A Analog
S Supply Voltage

Bibliography[edit]

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/packages/ft1&oldid=99921"
Facts about "Package FT1 - AMD"
RDF feed
designerAMD +
first launchedJanuary 4, 2011 +
instance ofpackage +
market segmentMobile +
microarchitectureBobcat +
nameFT1 +
packageFT1 +
package contacts413 +
package length19 mm (1.9 cm, 0.748 in) +
package typeOrganic Micro Ball Grid Array +
package width19 mm (1.9 cm, 0.748 in) +
tdp18 W (18,000 mW, 0.0241 hp, 0.018 kW) +