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Embedded G-Series T24L - AMD
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Embedded G-Series T24L
General Info
Model NumberT24L
Part NumberGET24LFQB12GVE
IntroductionMarch 1, 2011 (launched)
End-of-life2021-Q2 (last order)
2021-Q4 (last shipment)
General Specs
FamilyEmbedded G-Series
SeriesG-Series APU/CPU
Frequency1,000 MHz
Clock multiplier10
ISAx86-64 (x86)
Core NameeBrazos
Core Family20
Process40 nm
Die75 mm²
Word Size64 bit
Max SMP1-Way (Uniprocessor)
Tjunction0 °C – 90 °C
PackageFT1, UOB413 (FC-OBGA)
Dimension19 mm × 19 mm × 1.92 mm
Pitch0.8 mm

T24L is a 64-bit single-core x86 embedded microprocessor introduced by AMD in March 2011. This processor is a member of the AMD Embedded G-Series formerly codenamed "eBrazos" with CPU cores based on the Bobcat microarchitecture and is fabricated on a TSMC 40 nm process. The T24L operates at a base frequency of 1.0 GHz with a TDP of 5 W. It supports single-channel DDR3-1066 memory.


[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1 × 32 KiB2-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1 × 32 KiB8-way set associativewrite-back

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1 × 512 KiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeDDR3-1066
Supports ECCNo
Max Bandwidth8.53 GB/s
7.944 GiB/s
8,134.842 MiB/s
8,530 MB/s
0.00776 TiB/s
0.00853 TB/s


"eBrazos" processors integrate one 5-port, 8-lane PCIe Gen 1/2 (5 GT/s) controller. Four GPP lanes are configurable as up to four x4/x2/x1 wide (e.g. 1x2 + 2x1) links, the remaining four lanes are reserved for a UMI link to the chipset. The recommended AMD A50M "Hudson-M1" and A55E "Hudson-E1" controller hubs provide four PCIe Gen 1/2 lanes configurable as up to four x4/x2/x1 links, a 32-bit, 33 MHz PCI interface (A55E only), 6 × SATA Gen 1/2/3 (6 Gb/s), 14 × USB 1.1/2.0, 2 × USB 1.1, a Gb Ethernet MAC (A55E), HDA, LPC, SPI, SMBus, GPIO.

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 2.0
Max Lanes: 4
Configuration: 1x4/2x2/1x2+2x1/4x1



Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Embedded G-Series T24L - AMD#pcie +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
clock multiplier10 +
core count1 +
core family20 +
core nameeBrazos +
designerAMD +
die area75 mm² (0.116 in², 0.75 cm², 75,000,000 µm²) +
familyEmbedded G-Series +
first launchedMarch 1, 2011 +
full page nameamd/embedded/t24l +
has amd amd-v technologytrue +
has ecc memory supportfalse +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description16-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateMarch 1, 2011 +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory bandwidth7.944 GiB/s (8,134.842 MiB/s, 8.53 GB/s, 8,530 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels1 +
microarchitectureBobcat +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberT24L +
nameEmbedded G-Series T24L +
packageFT1 + and UOB413 +
part numberGET24LFQB12GVE +
process40 nm (0.04 μm, 4.0e-5 mm) +
seriesG-Series APU/CPU +
smp max ways1 +
supported memory typeDDR3-1066 +
tdp5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technologyCMOS +
thread count1 +
transistor count451,000,000 +
word size64 bit (8 octets, 16 nibbles) +