Edit Values
Embedded G-Series T48L
General Info
Designer	AMD
Manufacturer	TSMC
Model Number	T48L
Part Number	GET48LGBB22GVE
Market	Embedded
Introduction	March 1, 2011 (launched)
End-of-life	2021-Q2 (last order) 2021-Q4 (last shipment)
Shop	Amazon
General Specs
Family	Embedded G-Series
Series	G-Series APU/CPU
Frequency	1,400 MHz
Clock multiplier	14
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Bobcat
Core Name	eBrazos
Core Family	20
Process	40 nm
Transistors	451,000,000
Technology	CMOS
Die	75 mm²
Word Size	64 bit
Cores	2
Threads	2
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	18 W
Tjunction	0 °C – 90 °C
Packaging
Package	FT1, UOB413 (FC-OBGA)
Dimension	19 mm × 19 mm × 1.92 mm
Pitch	0.8 mm
Contacts	413

T48L is a 64-bit dual-core x86 embedded microprocessor introduced by AMD in March 2011. This processor is a member of the AMD Embedded G-Series formerly codenamed "eBrazos" with CPU cores based on the Bobcat microarchitecture and is fabricated on a TSMC 40 nm process. The T48L operates at a base frequency of 1.4 GHz with a TDP of 18 W. It supports single-channel DDR3-1066 memory.

Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2 × 32 KiB 2-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2 × 32 KiB 8-way set associative write-back L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     2 × 512 KiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC No Controllers 1 Channels 1 Max Bandwidth 8.53 GB/s 7.944 GiB/s 8,134.842 MiB/s 8,530 MB/s 0.00776 TiB/s 0.00853 TB/s

Expansions

"eBrazos" processors integrate one 5-port, 8-lane PCIe Gen 1/2 (5 GT/s) controller. Four GPP lanes are configurable as up to four x4/x2/x1 wide (e.g. 1x2 + 2x1) links, the remaining four lanes are reserved for a UMI link to the chipset. The recommended AMD A50M "Hudson-M1" and A55E "Hudson-E1" controller hubs provide four PCIe Gen 1/2 lanes configurable as up to four x4/x2/x1 links, a 32-bit, 33 MHz PCI interface (A55E only), 6 × SATA Gen 1/2/3 (6 Gb/s), 14 × USB 1.1/2.0, 2 × USB 1.1, a Gb Ethernet MAC (A55E), HDA, LPC, SPI, SMBus, GPIO.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 2.0 Max Lanes: 4 Configuration: 1x4/2x2/1x2+2x1/4x1

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4a Streaming SIMD Extensions 4a x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU AMD-V AMD Virtualization

Bibliography

• "Product Brief: AMD Embedded G-Series APU Platform", AMD Publ. #49282, 2013
• "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #43170, Rev. 3.13, February 17, 2012
• "Revision Guide for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #47534, Rev. 3.18, February 26, 2013
• Burgess, Brad. "“Bobcat” AMD’s New Low Power x86 Core Architecture", Hot Chips 22, August 24, 2010
• Burgess, Brad et al. (2011). Bobcat: AMD’s Low-Power x86 Processor. IEEE Micro. 31 (2): 16-25. doi:10.1109/MM.2011.2
• Foley, Denis et al. (2011). A Low-Power Integrated x86–64 and Graphics Processor for Mobile Computing Devices. IEEE JSSC. 47 (1): 220-231. doi:10.1109/JSSC.2011.2167776
• Rogers, Aaron; Kaplan, David; Quinnell, Eric; Kwan, Bill (2012). The Core-C6 (CC6) Sleep State of the AMD Bobcat x86 Microprocessor. ACM/IEEE ISLPED 2012. pp. 367-372. doi:10.1145/2333660.2333745
• "AMD Furthers Commitment to Embedded Customers With New Products and Expanded Support for Sales, Design and Software" (Press release). AMD.com. March 1, 2011.