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{{intel title|Process Technology History}}
 
{{intel title|Process Technology History}}
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This article details '''[[Intel]]'s [[semiconductor process technology]]''' history for research and posterity.
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This article details [[Intel]]'s semiconductor process technology history for research and posterity.
  
 
== Overview ==
 
== Overview ==
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[[File:intel process naming scheme.svg|400px]]
 
[[File:intel process naming scheme.svg|400px]]
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== Timeline ==
 
== Timeline ==
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[[File:intel 1micron yield.png|right|250px|thumb|[[1 µm]] vs [[500 nm]] yield]]
 
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[[File:intel historical 2yr process.png|250px|thumb|historical roadmap]]
 
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[[File:intel tech ramps 1um to 65nm.png|right|250px|thumb|Ramps from [[1 µm]] to [[65 nm]]]]
 
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[[File:intel roadmap past 180nm.png|right|250px|thumb|Roadmap past [[180 nm]]]]
 
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[[File:intel sram tests 130nm to 45nm.png|right|250px|thumb|SRAM test chips from [[130 nm]] to [[45 nm]]]]
 
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[[File:intel fab roadmap from 2003.png|250px|thumb|Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.]]
 
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[[File:intel sram density scaling.png|250px|thumb|[[65 nm]] to [[32 nm]] SRAM scaling]]
 
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[[File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]]]
 
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[[File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
 
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[[File:intel scaling roadmap to 5nm.png|250px|thumb|Intel roadmap from [[10 nm]] to [[5 nm]] and an advance packaging roadmap.]]
 
 
<div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
 
<div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
 
<table class="wikitable" style="text-align: center;">
 
<table class="wikitable" style="text-align: center;">
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</table>
 
</table>
 
</div>
 
</div>
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== Images ==
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<gallery>
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File:intel 1micron yield.png|right|250px|thumb|[[1 µm]] vs [[500 nm]] yield
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File:intel historical 2yr process.png|250px|thumb|historical roadmap
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File:intel tech ramps 1um to 65nm.png|right|250px|thumb|Ramps from [[1 µm]] to [[65 nm]]
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File:intel roadmap past 180nm.png|right|250px|thumb|Roadmap past [[180 nm]]
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File:intel sram tests 130nm to 45nm.png|right|250px|thumb|SRAM test chips from [[130 nm]] to [[45 nm]]
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File:intel fab roadmap from 2003.png|250px|thumb|Intel's fab roadmap from 2003 <!-- Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics -->
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File:intel sram density scaling.png|250px|thumb|[[65 nm]] to [[32 nm]] SRAM scaling
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File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]
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File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]
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File:intel scaling roadmap to 5nm.png|250px|thumb|Intel roadmap from [[10 nm]] to [[5 nm]] and an advance packaging roadmap
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</gallery>
  
 
== SRAM Scaling ==
 
== SRAM Scaling ==
 
For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.
 
For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.
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[[File:intel sram bit cell scaling.png|900px]]
 
[[File:intel sram bit cell scaling.png|900px]]

Latest revision as of 14:12, 8 March 2025


This article details Intel's semiconductor process technology history for research and posterity.

Overview[edit]

The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers. Finally, from the 45 nm node, Intel has switched to utilizing a high-κ material, therefore the oxide thickness shown refers to the equivalent oxide thickness instead.

Nomenclature[edit]

Intel has been using the same naming scheme for decades. All process technologies (including packaging technologies) begin with a 'P' followed by the wafer size and the process ID. Generally, the process ID is an auto-increment value with odd values generally reserved for SoC and I/O (low power) devices while the even values have been used for Intel premier line of high-performance processors.

intel process naming scheme.svg

Timeline[edit]

YearProcessNodeMLayersIntel µarchsGateInterconnectsAttributes
1972 PMOS I
(4004, 8008)		 10 µm 1 4004 Gate DielectricSiO2
Lg10.0 µm
1974 HMOS I
(4040)		 8 µm 1 4040 Gate DielectricSiO2
Lg8.0 µm
1976 HMOS II/III
(8080)		 6 µm 1 8080 Gate DielectricSiO2
Lg6.0 µm
1977 CHMOS I
(8086, 8088)		 3 µm 1 8085,
8086,
8088		 Tox70 nmGate DielectricSiO2
Vdd5 VSRAM1120 µm²
Lg3.0 µm
CPP7 µmMMP11 µm
1979 CHMOS II
(80186)		 2 µm 1 80186 Tox40 nmGate DielectricSiO2
Vdd5 VSRAM1740 µm²
Lg2.0 µm
CPP5.6 µmMMP8 µm
1982 P646
(CHMOS III)		 1.5 µm 1 80286,
80386		 Tox25 nmGate DielectricSiO2
Vdd5 VSRAM951.7 µm²
Lg1.5 µm
CPP4.0 µmMMP6.4 µm
1987 P648 1.0 µm 2 80486 ToxGate DielectricSiO2
Vdd5 VSRAM220 µm²
Lg1.0 µm
CPPMMP
1989 P650 0.8 µm 3 80486 Tox15 nmGate DielectricSiO2
Vdd4 VSRAM111 µm²
Lg800 nm
CPP1.7 µmMMP2 µm
1991 P652 0.6 µm 4 80486,
P5		 Tox8 nmGate DielectricSiO2
Vdd3.3 VSRAM
Lg600 nm
CPPMMP1.4 µm
1993 P852 0.5 µm 4 P5 Tox8 nmGate DielectricSiO2
Vdd3.3 VSRAM44 µm²
Lg500 nm
CPPMMP
1995 P854 0.35 µm 4 P6 Tox6 nmGate DielectricSiO2
Vdd2.5 VSRAM20.5 µm²
Lg350 nm
CPP920 nmMMP880 nm
1997 P856 0.25 µm 5 P6 Tox4.08 nmGate DielectricSiO2
Vdd1.8 VSRAM10.26 µm²
Lg200 nm
CPP500 nmMMP640 nm
1998 P856.5 0.25 µm 5 P6 Tox4.08 nmGate DielectricSiO2
Vdd1.8 VSRAM9.26 µm²
Lg200 nm
CPP475 nmMMP608 nm
1999 P858 0.18 µm 6 NetBurst intel 180nm gate.png Tox2.0 nmGate DielectricSiO2
Vdd1.6 VSRAM5.59 µm²
Lg130 nm
CPP480 nmMMP500 nm
2001 P860 0.13 µm 6 Pentium M intel 130nm gate.png intel 130nm gate interconnect.pngTox1.4 nmGate DielectricSiO2
Vdd1.4 VSRAM2.45 µm²
Lg70 nm
CPP336 nmMMP345 nm
2003 P1262 (CPU)
P1263 (SoC, I/O)		 90 nm 7 Pentium M intel 90nm gate.png intel 90nm gate interconnect.pngTox1.2 nmGate DielectricSiO2
Vdd1.2 VSRAM1.00 µm²
Lg50 nm
CPP260 nmMMP220 nm
2005 P1264 (CPU)
P1265 (SoC, I/O)		 65 nm 8 Core,
Modified Pentium M		 intel 65nm gate.png intel 65nm gate interconnect.pngTox1.2 nmGate DielectricSiO2
VddSRAM0.570 µm²
Lg35 nm
CPP220 nmMMP210 nm
2007 P1266 (CPU)
P1267 (SoC, I/O)		 45 nm 9 Penryn,
Nehalem		 intel 45nm gate.png intel 45nm gate interconnects.pngToxe1 nmGate DielectricHigh-κ
VddSRAM0.346 µm²
Lg25 nm
CPP160 nmMMP180 nm
2009 P1268 (CPU)
P1269 (SoC, I/O)		 32 nm 10 Westmere,
Sandy Bridge		 intel 32nm gate.png intel 32nm gate interconnect.pngToxe1 nmGate DielectricHigh-κ
Vdd0.75 VSRAM0.148 µm²
Lg30 nm
CPP112.5 nmMMP112.5 nm
2011 P1270 (CPU)
P1271 (SoC, I/O)		 22 nm 11 Ivy Bridge,
Haswell		 intel 22nm gate.png intel 22nm gate interconnect.pngToxe0.9 nmGate DielectricHigh-κ
Vdd0.75 VSRAM0.092 µm²
Lg26 nm
CPP90 nmMMP80 nm
Pfin60 nm
Wfin8 nmHfin34 nm
2014 P1272 (CPU)
P1273 (SoC, I/O)		 14 nm 12 Broadwell,
Skylake,
Kaby Lake,
Coffee Lake,
Cascade Lake,
Comet Lake,
Cooper Lake,
Rocket Lake		 intel 14nm gate top.png intel 14nm gate interconnect.pngToxeGate DielectricHigh-κ
Vdd0.70 VSRAM0.0499 µm²
Lg20 nm
CPP70 nmMMP52 nm
Pfin42 nm
Wfin8 nmHfin42-46 nm
2019 P1274 (CPU)
P1275 (SoC, I/O)		 10 nm 12-13 Cannon Lake,
Ice Lake,
Lakefield,
Tiger Lake		 ToxeGate DielectricHigh-κ
Vdd0.70 VSRAM0.0312 µm²
Lg18 nm
CPP54 nmMMP36 nm
Pfin34 nm
Wfin7 nmHfin44-55 nm
2021 P1276 (CPU)
P1277 (SoC, I/O)		 7 nm Intel 7 Alder Lake,
Raptor Lake,
Sapphire Rapids,
Emerald Rapids		 ToxeGate Dielectric
VddSRAM
Lg
CPPMMP
Pfin
WfinHfin
2023 P1278 (CPU)
P1279 (SoC, I/O)		 5 nm Intel
4 nm
3 nm
node		 Meteor Lake,
Granite Rapids		 ToxeGate Dielectric
VddSRAM
Lg
CPPMMP
Pfin
WfinHfin
2024 P1280 (CPU)
P1281 (SoC, I/O)		 3 nm TSMC
N3B		 Lunar Lake,
Arrow Lake		 ToxeGate Dielectric
VddSRAM
Lg
CPPMMP
Pfin
WfinHfin
2025 P1282 (CPU)
P1283 (SoC, I/O)		 2 nm Intel
18A		 Panther Lake,
Diamond Rapids		 ToxeGate Dielectric
VddSRAM
Lg
CPPMMP
Pfin
WfinHfin

Images[edit]

SRAM Scaling[edit]

For Intel, from 2 µm to 10 nm, SRAM 6T bit cells have had an average shrink of 0.496x in an attempt to maintain Moore's Law double density observation/requirement. Note that SRAM shrunk more significantly prior to the 65 nm process node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.

intel sram bit cell scaling.png

Other processes[edit]

Semiconductor Process history by company:

See also[edit]

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