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Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
 
Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
  
−
The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherit problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance.
+
The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance.
  
 
=== Larrabee ===
 
=== Larrabee ===
 
{{empty section}}
 
{{empty section}}

Revision as of 22:51, 26 June 2019

Below is a list of Intel microarchitectures:

CPU Microarchitectures

... further results
Intel CPU Microarchitectures
GeneralDetails
µarchIntroductionPhase-outProcessCoresPipeline
80386March 198419891,500 nm
1.5 μm
0.0015 mm
8048610 April 198919951,000 nm
1 μm
0.001 mm
, 800 nm
0.8 μm
8.0e-4 mm
, 600 nm
0.6 μm
6.0e-4 mm
P5April 1993October 1995600 nm
0.6 μm
6.0e-4 mm
P6October 1995December 2000350 nm
0.35 μm
3.5e-4 mm
, 250 nm
0.25 μm
2.5e-4 mm
NetBurst20 November 2000April 2006180 nm
0.18 μm
1.8e-4 mm
MercedJune 2001180 nm
0.18 μm
1.8e-4 mm
1
McKinley8 July 2002180 nm
0.18 μm
1.8e-4 mm
1, 2
Pentium M20032005130 nm
0.13 μm
1.3e-4 mm
, 90 nm
0.09 μm
9.0e-5 mm
Madison30 June 2003130 nm
0.13 μm
1.3e-4 mm
1
Madison 9M8 November 2004130 nm
0.13 μm
1.3e-4 mm
1
Modified Pentium M2006200865 nm
0.065 μm
6.5e-5 mm
CoreApril 2006May 200965 nm
0.065 μm
6.5e-5 mm
Montecito18 July 200690 nm
0.09 μm
9.0e-5 mm
1, 2
PolarisFebruary 200765 nm
0.065 μm
6.5e-5 mm
809
Montvale31 October 200790 nm
0.09 μm
9.0e-5 mm
1, 2
PenrynNovember 2007September 200845 nm
0.045 μm
4.5e-5 mm
Bonnell2 March 2008201145 nm
0.045 μm
4.5e-5 mm
1, 21619
NehalemAugust 2008March 201045 nm
0.045 μm
4.5e-5 mm
Rock CreekDecember 200945 nm
0.045 μm
4.5e-5 mm
48
WestmereJanuary 2010August 201132 nm
0.032 μm
3.2e-5 mm
Tukwila8 February 201065 nm
0.065 μm
6.5e-5 mm
1, 2
Knights Ferry31 May 2010201145 nm
0.045 μm
4.5e-5 mm
32
Sandy Bridge (client)13 September 2010November 201232 nm
0.032 μm
3.2e-5 mm
2, 41419
Saltwell2011201332 nm
0.032 μm
3.2e-5 mm
1, 216
Knights Corner2011201322 nm
0.022 μm
2.2e-5 mm
57, 60, 61
Ivy Bridge4 May 2011April 201322 nm
0.022 μm
2.2e-5 mm
Poulson8 November 201232 nm
0.032 μm
3.2e-5 mm
1, 2
Silvermont2013201522 nm
0.022 μm
2.2e-5 mm
1, 2, 4, 81214
Haswell4 June 2013201522 nm
0.022 μm
2.2e-5 mm
2, 4, 6, 8, 16, 10, 12, 14, 181419
BroadwellOctober 201414 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 221419
Airmont2015201714 nm
0.014 μm
1.4e-5 mm
1, 2, 4, 81214
Skylake (client)5 August 201514 nm
0.014 μm
1.4e-5 mm
2, 41419
Goldmont30 August 201614 nm
0.014 μm
1.4e-5 mm
2, 4, 8, 12, 161214
Kaby Lake30 August 201614 nm
0.014 μm
1.4e-5 mm
2, 41419
Kittson201722 nm
0.022 μm
2.2e-5 mm
1, 2
Skylake (server)4 May 201714 nm
0.014 μm
1.4e-5 mm
4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 281419
Coffee Lake5 October 201714 nm
0.014 μm
1.4e-5 mm
1419
Goldmont Plus11 December 201714 nm
0.014 μm
1.4e-5 mm
2, 4
Knights Mill18 December 20179 August 201914 nm
0.014 μm
1.4e-5 mm
Palm Cove201810 nm
0.01 μm
1.0e-5 mm
21419
Amber LakeApril 201814 nm
0.014 μm
1.4e-5 mm
21419
Whiskey LakeApril 201841419
Cannon Lake15 May 201810 nm
0.01 μm
1.0e-5 mm
21419
Cascade Lake201914 nm
0.014 μm
1.4e-5 mm
2, 4, 6, 8, 10, 12, 16, 18, 20, 22, 24, 26, 28, 32, 48, 561419
Tremont201910 nm
0.01 μm
1.0e-5 mm
Snow Ridge201910 nm
0.01 μm
1.0e-5 mm
Sunny Cove2019202110 nm
0.01 μm
1.0e-5 mm
2, 4, 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 401419
Lakefield201922 nm
0.022 μm
2.2e-5 mm
, 10 nm
0.01 μm
1.0e-5 mm
5
Ice Lake (client)27 May 201910 nm
0.01 μm
1.0e-5 mm
2, 41419
Willow Cove202010 nm
0.01 μm
1.0e-5 mm
2, 4, 6, 81419

GPU Microarchitectures

Intel GPU Microarchitectures
GeneralDetails
µarchIntroductionPhase-outProcess
Gen11998
Gen22002
Gen32004
Gen3.5200590 nm
0.09 μm
9.0e-5 mm
Gen4200665 nm
0.065 μm
6.5e-5 mm
Gen53 June 200845 nm
0.045 μm
4.5e-5 mm
Larrabee12 August 2008201032 nm
0.032 μm
3.2e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
Gen5.75January 201045 nm
0.045 μm
4.5e-5 mm
Gen613 September 201032 nm
0.032 μm
3.2e-5 mm
Gen74 May 201122 nm
0.022 μm
2.2e-5 mm
Gen7.54 June 201322 nm
0.022 μm
2.2e-5 mm
Gen8October 201414 nm
0.014 μm
1.4e-5 mm
Gen95 August 201514 nm
0.014 μm
1.4e-5 mm
Gen9.530 August 201614 nm
0.014 μm
1.4e-5 mm
Gen11201810 nm
0.01 μm
1.0e-5 mm
Gen10201810 nm
0.01 μm
1.0e-5 mm
Arctic Sound202010 nm
0.01 μm
1.0e-5 mm
Gen12202010 nm
0.01 μm
1.0e-5 mm
Jupiter Sound202210 nm
0.01 μm
1.0e-5 mm

Many-core

Under construction icon-blue.svg This article is a work in progress!

Initial effort & Polaris

Intel actual large effort research into the area of many-core started after the February 2004 Intel Developer Forum following Pradeep Dubey famous keynote titled "The Era of Tera." Around the 2004-2005 Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the Tera-scale Computing Research Program which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.

The first product to come directly from that project was Polaris, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a mesh topology. Fabricated on a 65 nm process, the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. 3D stacked SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 teraFLOPS of sustained performance.

Larrabee

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