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Cortex-A55 - Microarchitectures - ARM Holdings
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Cortex-A55 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC, Samsung, GlobalFoundries, SMIC
IntroductionMay 29, 2017
Process16 nm, 14 nm, 10 nm, 7 nm
Core Configs1, 2, 3, 4
Reg RenamingNo
ExtensionsFPU, NEON, TrustZone
L1I Cache8-64 KiB/core
2-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256 KiB/core
L3 Cache0-4 MiB/Cluster

Cortex-A55 is an ultra-high efficiency microarchitecture designed by ARM Holdings as a successor to the Cortex-A53. The Cortex-A55, which implemented the ARMv8.2 ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on Cortex-A75) in DynamIQ big.LITTLE configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

Process Technology[edit]

The Cortex-A55 was primarily designed to make use of TSMC's 16 nm process with a 7 nm optimized version set for the end of 2017 or early 2018.


The Cortex-A55 is an improved version of the A53 which introduces a number of performance enhancements as well as designed to be implemented based on ARM's DynamIQ big.LITTLE design.

Key changes from Cortex-A53[edit]

  • Higher performance (ARM claims: up to 2x mem perf, up to 15% less power from A53)
  • Implements ARMv8.2 (from ARMv8.0)
  • Designed as a cluster of 1 to 8 cores
    • Adds DynamIQ Shared Unit (DSU)
  • Branch predictor was re-written
  • Memory subsystem
    • L2
      • L2 cache is now private to each core (from shared between all cores)
      • Latency was cut by half
      • Now runs at the same frequency as the core
      • Configurable size from 64 KiB to 256 KiB
    • L3
      • A new L3 cache was introduced
      • Shared by all cores
      • Configurable size: 0 MiB - 4 MiB
  • NEON is improved


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All Cortex-A55 Chips[edit]

 List of all Cortex-A55 Chips
 Main processorIGP
ModelLaunchedDesignerFamilyCoreCTL2$L3$FrequencyMax MemDesignerNameFrequency
9810Samsung, ARM HoldingsExynosMongoose M3, Cortex-A55882.9 GHz
2,900 MHz
2,900,000 kHz
, 1.9 GHz
1,900 MHz
1,900,000 kHz
Count: 1
codenameCortex-A55 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a55 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +, Samsung +, GlobalFoundries + and SMIC +
microarchitecture typeCPU +
nameCortex-A55 +
pipeline stages8 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +