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Hexagon - Microarchitectures - Qualcomm
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Hexagon µarch
General Info
Arch TypeDSP
DesignerQualcomm
ManufacturerTSMC
Process65 - 28
Pipeline
Type4-way VLIW, 4-thread SMT
OoOENo
Decode4-way
Instructions
ExtensionsHVX

Hexagon is VLIW DSP architecture designed by Qualcomm. It is used in many Qualcomm's SoC as Audio, Sensor or Compute coprocessor, and in the many Qualcomm modems. Usually runs some kind of Real-time OS, optimized for low power and small chip area. Supports of simultaneous execution of several threads, with interleaved multithreading in V1-V4 and dynamic multithreading since V5.

Architecture[edit]

Versions of Hexagon Architecture:

  • V1 - 65nm, October 2006
  • V2 - 65nm, December 2007
  • V3M - 45nm, June 2009
  • V3C - 45nm, August 2009
  • V3L - 45nm, November 2009
  • V4M - 28nm, December 2010
  • V4C - 28nm, December 2010
  • V4L - 28nm, April 2011
  • V5A - 28nm, December 2012
  • V5H - 28nm, December 2012
  • Hexagon 400
    • Only Fixed Point
  • Hexagon 500
    • Floating Point
  • Hexagon 600
    • Hexagon Vector eXtensions (HVX) added

Overview[edit]

Block Diagram[edit]

Memory Hierarchy[edit]

  • L1I Cache:
  • L1D Cache:
  • L2 Cache:
  • L3 Cache:
  • TLBs:

Core[edit]

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Die[edit]

All SoCs using Hexagon[edit]

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References[edit]

Documents[edit]

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codenameHexagon +
designerQualcomm +
full page namequalcomm/microarchitectures/hexagon +
instance ofmicroarchitecture +
manufacturerTSMC +
nameHexagon +