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Skylake (server) µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMay 4, 2017
Process14 nm
Core Configs4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-16, x86-32, x86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache1 MiB/core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesSkylake X, Skylake SP
Succession
Contemporary
Skylake (client)

Skylake (SKL) Server Configuration is Intel's successor to Broadwell, an enhanced 14nm+ process microarchitecture for enthusiasts and servers. Skylake succeeded Broadwell. Skylake is the "Architecture" phase as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel.

For desktop enthusiasts, Skylake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.

There are a fair number of major differences in the Skylake server configuration vs the client configuration.

Codenames[edit]

See also: Client Skylake's Codenames
Core Abbrev Target
Skylake X SKL-X High-end desktops & enthusiasts market
Skylake SP SKL-SP Server Scalable Processors

Brands[edit]

See also: Client Skylake's Brands
New Xeon branding

Intel introduced a number of new server chip families with the introduction of Skylake SP as well as a new enthusiasts family with the introduction of Skylake X.

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 AVX-512 TBT ECC
core i7 logo (2015).png Core i7 Enthusiasts/High Performance (X) 6 - 8
core i9x logo.png Core i9 Enthusiasts/High Performance 10 - 18
Logo Family General Description Differentiating Features
Cores HT TBT AVX-512 AVX-512 Units UPI links Scalability
xeon bronze (2017).png Xeon Bronze Entry-level performance /
Cost-sensitive
6 - 8 1 2 Up to 2
xeon silver (2017).png Xeon Silver Mid-range performance /
Efficient lower power
4 - 12 1 2 Up to 2
xeon gold (2017).png Xeon Gold 5000 High performance 4 - 14 1 2 Up to 4
Xeon Gold 6000 Higher performance 6 - 22 2 3 Up to 4
xeon platinum (2017).png Xeon Platinum Highest performance / flexibility 4 - 28 2 3 Up to 8

Release Dates[edit]

Skylake-based Core X was introduced in May 2017 while Skylake SP was introduced in July 2017.

Process Technology[edit]

Main article: Kaby Lake § Process Technology

Unlike mainstream Skylake models, all Skylake server configuration models are fabricated on Intel's enhanced 14+ nm process which is used by Kaby Lake.

Compatibility[edit]

Vendor OS Version Notes
Microsoft Windows Windows Server 2008 Support
Windows Server 2008 R2
Windows Server 2012
Windows Server 2012 R2
Windows Server 2016
Linux Linux Kernel 3.19 Initial Support (MPX support)

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake-avx512 -mtune=skylake-avx512
GCC -march=skylake-avx512 -mtune=skylake-avx512
LLVM -march=skylake-avx512 -mtune=skylake-avx512
Visual Studio /arch:AVX2 /tune:skylake

CPUID[edit]

Core Extended
Family
Family Extended
Model
Model
X 0 0x6 0x5 0xE
Family 6 Model 94
SP 0 0x6 0x5 0x5
Family 6 Model 85

Architecture[edit]

Skylake server configuration introduces a number of significant changes from both Intel's previous microarchitecture, Broadwell, as well as the Skylake (client) architecture. Unlike client models, Skylake servers and HEDT models will still incorporate the fully integrated voltage regulator (FIVR) on-die. Those chips also have an entirely new multi-core architecture along with a new mesh topology interconnect network (from ring topology).

Key changes from Broadwell[edit]

skylake sp buffer windows.png
  • Improved "14 nm+" process (see Kaby Lake § Process Technology)
  • Omni-Path Architecture (OPA)
  • Mesh architecture
  • Chipset
    • WellsburgLewisburg
    • Bus/Interface to Chipset
      • DMI 3.0 (from 2.0)
        • Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane
        • Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
    • DMI upgraded to Gen3
  • Core
    • Front End
      • LSD is disabled (Likely due to a bug; see § Front-end for details)
      • Larger legacy pipeline delivery (5 µOPs, up from 4)
        • Another simple decoder has been added.
      • Allocation Queue (IDQ)
        • Larger delivery (6 µOPs, up from 4)
        • 2.28x larger buffer (64/thread, up from 56)
        • Partitioned for each active threads (from unified)
      • Improved branch prediction unit
        • reduced penalty for wrong direct jump target
        • No specifics were disclosed
      • µOP Cache
        • instruction window is now 64 Bytes (from 32)
        • 1.5x bandwidth (6 µOPs/cycle, up from 4)
    • Execution Engine
      • Larger re-order buffer (224 entries, up from 192)
      • Larger scheduler (97 entries, up from 64)
        • Larger Integer Register File (180 entries, up from 168)
    • Back-end
      • Port 4 now performs 512b stores (from 256b)
      • Port 0 & Port 1 can now be fused to perform AVX-512
      • Port 5 now can do full 512b operations (not on all models)
    • Memory Subsystem
      • Larger store buffer (56 entries, up from 42)
      • Page split load penalty reduced 20-fold
      • Larger Write-back buffer
      • Store is now 64B/cycle (from 32B/cycle)
      • Load is now 2x64B/cycle (from 2x32B/cycle)
  • Memory
    • L2$
      • Increased to 1 MiB/core (from 250 KiB/core)
    • L3$
      • Was made non-inclusive (from inclusive)
      • Reduced to 1.375 MiB/core (from 2.5 MiB/core)
    • DRAM
      • hex-channel DDR4-2666 (from quad-channel)
  • TLBs
    • ITLB
      • 4 KiB page translations was changed from 4-way to 8-way associative
    • STLB
      • 4 KiB + 2 MiB page translations was changed from 6-way to 12-way associative
    • DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals)
  • Testability
    • New support for Direct Connect Interface (DCI), a new debugging transport protocol designed to allow debugging of closed cases (e.g. laptops, embedded) by accessing things such as JTAG through any USB 3 port.

CPU changes[edit]

  • Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).
  • MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.
  • ADC and SBB have throughput of 1 op/cycle, same as Haswell.
  • Vector moves have throughput of 4 op/cycle (move elimination).
  • Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.
  • Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.
  • Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.
  • Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.
  • Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.
  • Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle.
  • vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op.
  • Throughput of some MMX ALU ops (such as PAND mm1, mm2) is decreased to 2 or 1 op/cycle (users are expected to use wider SSE/AVX registers instead).

New instructions[edit]

See also: Client Skylake's New instructions

Skylake server introduced a number of new instructions:

  • SGX1 - Software Guard Extensions, Version 1
  • MPX -Memory Protection Extensions
  • XSAVEC - Save processor extended states with compaction to memory
  • XSAVES - Save processor supervisor-mode extended states to memory.
  • CLFLUSHOPT - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
  • AVX-512, specifically:
  • PKU - Memory Protection Keys for Userspace
  • PCOMMIT - PCOMMIT instruction
  • CLWB - CLWB instruction

Block Diagram[edit]

Entire SoC Overview[edit]

Note that the LCC die is identical without the two bottom rows. The XCC (28-core) die has one additional row and two additional columns of cores. Otherwise the die is identical.

skylake sp hcc block diagram.svg

  • CHA - Caching and Home Agent
  • SF - Snooping Filter
Individual Core[edit]

skylake server block diagram.svg

Memory Hierarchy[edit]

skylake x memory changes.png

Some major organizational changes were done to the cache hierarchy in Skylake server configuration vs Broadwell/Haswell. The memory hierarchy for Skylake's server and HEDT processors has been rebalanced. Note that the L3 is now non-inclusive and some of the SRAM from the L3 cache was moved into the private L2 cache.

  • Cache
    • L0 µOP cache:
      • 1,536 µOPs, 8-way set associative
        • 32 sets, 6-µOP line size
        • statically divided between threads, per core, inclusive with L1I
    • L1I Cache:
      • 32 KiB, 8-way set associative
        • 64 sets, 64 B line size
        • shared by the two threads, per core
    • L1D Cache:
      • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
      • 4 cycles for fastest load-to-use (simple pointer accesses)
        • 5 cycles for complex addresses
      • 128 B/cycle load bandwidth
      • 64 B/cycle store bandwidth
      • Write-back policy
    • L2 Cache:
      • Unified, 1 MiB, 16-way set associative
      • 64 B line size
      • Non-inclusive
      • 64 B/cycle bandwidth to L1$
      • Write-back policy
      • 14 cycles latency
    • L3 Cache:
      • 1.375 MiB/s, shared across all cores
        • Note that some models have non-default cache sizes which are larger due to some disabled cores
      • 64 B line size
      • 11-way set associative
      • Non-Inclusive
      • Write-back policy
      • 50-70 cycles latency

Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

  • TLBs:
    • ITLB
      • 4 KiB page translations:
        • 128 entries; 8-way set associative
        • dynamic partitioning
      • 2 MiB / 4 MiB page translations:
        • 8 entries per thread; fully associative
        • Duplicated for each thread
    • DTLB
      • 4 KiB page translations:
        • 64 entries; 4-way set associative
        • fixed partition
      • 2 MiB / 4 MiB page translations:
        • 32 entries; 4-way set associative
        • fixed partition
      • 1G page translations:
        • 4 entries; fully associative
        • fixed partition
    • STLB
      • 4 KiB + 2 MiB page translations:
        • 1536 entries; 12-way set associative
        • fixed partition
      • 1 GiB page translations:
        • 16 entries; 4-way set associative
        • fixed partition

Overview[edit]

skylake sp (superset features).png

Skylake-based servers have been entirely re-architected to meet the need for increased scalabiltiy and performance all while meeting power requirements. A superset model is shown on the right. Skylake-based servers are the first mainstream servers to make use of Intel's new mesh interconnect architecture, an architecture that was previously explored, experimented with, and enhanced with Intel's Phi many-core processors. Those processors are offered from 4 cores up to 28 cores with 8 to 56 threads. With Skylake, Intel now has a separate core architecture for those chips which incorporate a plethora of new technologies and features including support for the new AVX-512 instruction set extension.

All models incorporate 6 channels of DDR4 supporting up to 12 DIMMS for a total of 768 GiB (with extended models support 1.5 TiB). For I/O all models incorporate 48x (3x16) lanes of PCIe 3.0. There is an additional x4 lanes PCIe 3.0 reserved exclusively for DMI for the the Lewisburg chipset. For a selected number of models (specifically those with F suffix) have an Omni-Path Host Fabric Interface (HFI) on-package (see Integrated Omni-Path).

Skylake processors are designed for scalability, supporting 2-way, 4-way, and 8-way multiprocessing through Intel's new Ultra Path Interconnect (UPI) interconnect links, with two to three links being offered (see § Scalability). High-end models have node controller support allowing higher way (e.g., 32-way multiprocessing).

Core[edit]

Overview[edit]

Skylake shares most of the development vectors with its predecessor while introducing a one of new constraint. The overall goals were:

  • Performance improvements - the traditional way of milking more performance by increasing the instructions per cycle as well as clock frequency.
  • Power efficiency - reduction of power for all functional blocks
  • Security enhancements - new security features are implemented in hardware in the core
  • Configurability

Configurability[edit]

skylake master core configs.svg

Intel has been experiencing a growing divergence in functionality over the last number of iterations of their microarchitecture between their mainstream consumer products and their high-end HPC/server models. Traditionally, Intel has been using the same exact core design for everything from their lowest end value models (e.g. Celeron) all the way up to the highest-performance enterprise models (e.g. Xeon E7). While the two have fundamentally different chip architectures, they use the same exact CPU core architecture as the building block.

This design philosophy has changed with Skylake. In order to better accommodate the different functionalities of each segment without sacrificing features or making unnecessary compromises Intel went with a configurable core. The Skylake core is a single development project, making up a master superset core. The project result in two derivatives: one for servers (the substance of this article) and one for clients. All mainstream models (from Celeron/Pentium all the way up to Core i7/Xeon E3) use the client core configuration. Server models (e.g. Xeon Gold/Xeon Platinum) are using the new server configuration instead.

The server core is considerably larger than the client one, featuring Advanced Vector Extensions 512 (AVX-512). Skylake servers support what was formerly called AVX3.2 (AVX512F + AVX512CD + AVX512BW + AVX512DQ + AVX512VL). Additionally, those processors Memory Protection Keys for Userspace (PKU), PCOMMIT, and CLWB.

Pipeline[edit]

The Skylake core focuses on extracting performance and reducing power through a number of key ways. Intel builds Skylake on previous microarchitectures, descendants of Sandy Bridge. For the core to increase the overall performance, Intel focused on extracting additional parallelism.

Front-end[edit]

For the most part, with the exception of the LSD, the front-end of the Skylake server core is identical to the client configuration. For in-depth detail of the Skylake front-end see Skylake (client) § Front-end.

The only major difference in the front-end from the client core configuration is the LSD. The Loop Stream Detector (LSD) has been disabled. While the exact reason is not known, it might be related to a severe issue that was experienced by the OCaml Development Team. The issue was patched via microcode on the client platform, however this change might indicate it was possibly disabled on there as well. The exact implications of this are unknown.

Execution engine[edit]

The Skylake server configuration core back-end is identical to the client configuration up to the scheduler. For in-depth detail of the Skylake back-end up to that point, see Skylake (client) § Execution engine.

Scheduler & 512-SIMD addition[edit]
skylake scheduler server.svg

The scheduler itself was increased by 50%; with up to 97 entries (from 64 in Broadwell) being competitively shared between the two threads. Skylake continues with a unified design; this is in contrast to designs such as AMD's Zen which uses a split design each one holding different types of µOPs. Scheduler includes the two register files for integers and vectors. It's in those register files that output operand data is store. In Skylake, the integer register file was also slightly increased from 160 entries to 180.

skylake sp added cach and vpu.png

This is the first implementation to incorporate AVX-512, a 512-bit SIMD x86 instruction set extension. Intel introduced AVX-512 in two different ways:

In the simple implementation, the variants used in the entry-level and mid-range Xeon servers, AVX-512 fuses Port 0 and Port 1 to form a 512-bit unit. Since those two ports are 256-wide, an AVX-512 option that is dispatched by the scheduler to port 0 will execute on both ports. Note that unrelated operations can still execute in parallel. For example, an AVX-512 operation and an Int ALU operation may execute in parallel - the AVX-512 is dispatched on port 0 and use the AVX unit on port 1 as well and the Int ALU operation will execute independently in parallel on port 1.

In the high-end and highest performance Xeons, Intel added a second dedicated AVX-512 unit in addition to the fused Port0-1 operations described above. The dedicated unit is situated on Port 5.

Physically, Intel added 768 KiB L2 cache and the second AVX-512 VPU externally to the core.

Scheduler Ports & Execution Units[edit]
Scheduler Ports Designation
Port 0Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops512-bit Vect ALU/Shift/Mul/FMA
FP Add, Multiply, FMA
Integer/FP Division and Square Root
AES Encryption
Branch2
Port 1Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning
FP Add, Multiply, FMA
Port 5Integer/Vector Arithmetic, Logic512-bit Vect ALU/Shift/Mul/FMA
Vector Permute
x87 FP Add, Composite Int, CLMUL
Port 6Integer Arithmetic, Logic, Shift
Branch
Port 2Load, AGU
Port 3Load, AGU
Port 4Store, AGU
Port 7AGU

Memory subsystem[edit]

skylake-sp memory.svg

Skylake's memory subsystem is in charge of the loads and store requests and ordering. Since Haswell, it's possible to sustain two memory reads (on ports 2 and 3) and one memory write (on port 4) each cycle. Each memory operation can be of any register size up to 512 bits. Skylake memory subsystem has been improved. The store buffer has been increased by 42 entries from Broadwell to 56 for a total of 128 simultaneous memory operations in-flight or roughly 60% of all µOPs. Special care was taken to reduce the penalty for page-split loads; previously scenarios involving page-split loads were thought to be rarer than they actually are. This was addressed in Skylake with page-split loads are now made equal to other splits loads. Expect page split load penalty down to 5 cycles from 100 cycles in Broadwell. The average latency to forward a load to store has also been improved and stores that miss in the L1$ generate L2$ requests to the next level cache much earlier in Skylake than before.

The L2 to L1 bandwidth in Skylake is the same as Haswell at 64 bytes per cycle in either direction. Note that one operation can be done each cycle; i.e., the L1 can either receive data from the L1 or send data to the Load/Store buffers each cycle, but not both. Latency from L2$ to L3$ has also been increased from 4 cycles/line to 2 cycles/line.

The medium level cache (MLC) and last level cache (LLC) was rebalanced. Traditionally, Intel had a 256 KiB L2 cache which was duplicated along with the L1s over in the LLC which was 2.5 MiB. That is, prior to Skylake, the 256 KiB L2 cache actually took up 512 KiB of space for a total of 2.25 mebibytes effective cache per core. In Skylake Intel doubled the L2 and quadrupled the effective capacity to 1 MiB while decreasing the LLC to 1.375 MiB. The LLC is also now made non-inclusive, i.e., the L2 may or may not be in the L3 (no guarantee is made); what stored where will depend on the particular access pattern of the executing application, the size of code and data accessed, and the inter-core sharing behavior. Having an inclusive L3 makes cache coherence considerably easier to implement. Snooping only requires checking the L3 cache tags to know if the data is on board and in which core. It also makes passing data around a bit more efficient. It's currently unknown what mechanism is being used to reduce snooping. In the past, Intel has discussed a couple of additional options they were researching such as NCID (non-inclusive cache, inclusive directory architecture). It's possible that a NCID is being used in Skylake or a related derivative. These changes also mean that software optimized for data placing in the various caches needs to be revised for the new changes, particularly in situations where data is not shared, the overall capacity can be treated as L2+L3 for a total of 2.375 MiB.

New Technologies[edit]

Software Guard Extension (SGX)[edit]

Main article: Intel's Software Guard Extension

Software Guard Extension (SGX) is a new inter-software guard x86 extension that allows software in user-level mode to create isolated secure environments called "enclaves" for storing data or code. Data and code stored in enclaves are protected from external processes including code executing with higher privileges including the operating system or a hypervisor (including all forms of debugging).

Memory Protection Extension (MPX)[edit]

Main article: Intel's Memory Protection Extension

Memory Protection Extension (MPX) is a new x86 extension that offers a hardware-level bound checking implementation. This extension allows an application to define memory boundaries for allocated memory areas. The processors can then check all proceeding memory accesses against those boundaries to ensure accesses are not out of bound. A program accessing a boundary-marked buffer out of buffer will generate an exception.

Key Protection Technology (KPT)[edit]

Key Protection Technology (KPT) is designed to help secure sensitive private keys in hardware at runtime. KPT augments QuickAssist Technology (QAT) hardware crypto accelerators with run-time storage of private keys using Intel's existing Platform Trust Technology (PTT), thereby allowing high throughput hardware security acceleration. The QAT accelerators are all integrated onto Intel's new Lewisburg chipset along with the Converged Security Manageability Engine (CSME) which implements Intel's PTT. The CSME is linked through a private hardware link that is invisible to x86 software and simple hardware probes.

Memory Protection Keys for Userspace (PKU)[edit]

Memory Protection Keys for Userspace (PKU also PKEYs) is an extension that provides a mechanism for enforcing page-based protections - all without requiring modification of the page tables when an application changes protection domains. PKU introduces 16 keys by re-purposing the 4 ignored bits from the page table entry.

Mode-Based Execute (MBE) Control[edit]

Mode-Based Execute (MBE) is an enhancement to the Extended Page Tables (EPT) that provides finer level of control of execute permissions. With MBE the previous Execute Enable (X) bit is turned into Excuse Userspace page (XU) and Execute Supervisor page (XS). The processor selects the mode based on the guest page permission. With proper software support, hypervisors can take advantage of this as well to ensure integrity of kernel-level code.

Mesh Architecture[edit]

skylake sp xcc die config.png

On the previous number of generations, Intel has been adding cores onto the die and connecting them via a ring architecture. This was sufficient until recently. With each generation, the added cores increased the access latency while lowering the available bandwidth per core. Intel mitigated this problem by splitting up the die into two halves each on its own ring. This reduced hopping distance and added additional bandwidth but it did not solve the growing fundamental inefficiencies of the ring architecture.

This was completely addressed with the new mesh architecture that is implemented in the Skylake server processors. The mesh is arranged as a matrix of vertical and horizontal communication paths which allow communication to take the shortest path to the correct node. The new mesh architecture implements a modular design for the routing resources in order to remove the various bottlenecks. That is, the mesh architecture now integrates the caching agent, the home agent, and the IO subsystem on the mesh interconnect distributed across all the cores. Each core now has its own associated LLC slice as well as the snooping filter and the Caching and Home Agent (CHA). Additional nodes such as the two memory controllers, the Ultra Path Interconnect (UPI) nodes and PCIe are not independent node on the mesh as well and they now behave identically to any other node/core in the network. This means that in addition to the performance increase expected from core-to-core and core-to-memory latency, there should be substantial increase in I/O performance. The CHA which is found on each of the LLC slices now maps addresses being accessed to the specific LLC bank, memory controller, or I/O subsystem. This provides the necessary information required for the routing to take place.

Cache Coherency[edit]

Given the new mesh architecture, new tradeoffs were involved. The new UPI inter-socket links are a valuable resource that could bottlenecked when flooded with unnecessary cross-socket snoop requests. There's also considerably higher memory bandwidth with Skylake which can impact performance. As a compromise, the previous four snoop modes (no-snoop, early snoop, home snoop, and directory) have been reduced to just directory-base coherency. This also alleviates the implementation complexity (which is already complex enough in itself).

snc clusters.png

It should be pointed out that the directory-base coherency optimizations that were done in previous generations have been furthered improved with Skylake - particularly OSB, HitME cache, IO directory cache. Skylake maintained support for Opportunistic Snoop Broadcast (OSB) which allows the network to opportunistically make use of the UPI links when idle or lightly loaded thereby avoiding an expensive memory directory lookup. With the mesh network and distributed CHAs, HitME is now distributed and scales with the CHAs, enhancing the speeding up of cache-to-cache transfers (Those are your migratory cache lines that frequently get transferred between nodes). Specifically for I/O operations, the I/O directory cache (IODC), which was introduced with Haswell, improves stream throughput by eliminating directory reads for InvItoE from snoopy caching agent. Previously this was implemented as a 64-entry directory cache to complement the directory in memory. In Skylake, with a distributed CHA at each node, the IODC is implemented as an eight-entry directory cache per CHA.

Sub-NUMA Clustering[edit]

In previous generations Intel had a feature called cluster-on-die (COD) which was introduced with Haswell. With Skylake, there's a similar feature called sub-NUMA cluster (SNC). With a memory controller physically located on each side of the die, SNC allows for the creation of two localized domains with each memory controller belonging to each domain. The processor can then map the addresses from the controller to the distributed home ages and LLC in its domain. This allows executing code to experience lower LLC and memory latency within its domain compared to accesses outside of the domain.

It should be pointed out that in contrast to COD, SNC has a unique location for every adddress in the LCC and is never duplicated across LLC banks (previously, COD cache lines could have copies). Additionally, on multiprocessor system, address mapped to memory on remote sockets are still uniformally distributed across all LLC banks irrespective of the localized SNC domain.

Scalability[edit]

See also: QuickPath Interconnect and Ultra Path Interconnect

In the last couple of generations, Intel has been utilizing QuickPath Interconnect (QPI) which served as a high-speed point-to-point interconnect. QPI has been replaced by the Ultra Path Interconnect (UPI) which is higher-efficiency coherent interconnect for scalable systems, allowing multiple processors to share a single shared address space. Depending on the exact model, each processor can have either either two or three UPI links connecting to the other processors.

UPI links eliminate some of the scalability limitations that surfaced in QPI over the past few microarchitecture iterations. They use directory-based home snoop coherency protocol and operate at up either 10.4 GT/s or 9.6 GT/s. This is quite a bit different form previous generations. In addition to the various improvements done to the protocol layer, Skylake SP now implements a distributed CHA that is situated along with the LLC bank on each core. It's in charge of tracking the various requests form the core as well as responding to snoop requests from both local and remote agents. The ease of distributing the home agent is a result of Intel getting rid of the requirement on preallocation of resources at the home agent. This also means that future architectures should be able to scale up well.

Depending on the exact model, Skylake processors can scale from 2-way all the way up to 8-way multiprocessing. Note that the high-end models that support 8-way multiprocessing also only come with three UPI links for this purpose while the lower end processors can have either two or three UPI links. Below are the typical configurations for those processors.


2-way SMP; 2 UPI links

skylake sp 2-way 2 upi.svg
2-way SMP; 3 UPI links

skylake sp 2-way 3 upi.svg


4-way SMP; 2 UPI links

skylake sp 4-way 2 upi.svg
4-way SMP; 3 UPI links

skylake sp 4-way 3 upi.svg


8-way SMP; 3 UPI links

skylake sp 8-way 3 upi.svg

Integrated Omni-Path[edit]

See also: Intel's Omni-Path
IFT (Internal Faceplate Transition) Carrier

A number of Skylake SP models (specifically those with the "F" suffix) incorporate the Omni-Path Host Fabric Interface (HFI) on-package. This was previously done with the Knights Landing ("F" suffixed) models. This, in addition to improving cost and power efficiencies, also eliminates the dependency on the x16 PCIe lanes on the motherboard. With the HFI on package, the chip can be plugged in directly to the IFT (Internal Faceplate Transition) carrier via a separate IFP (Internal Faceplate-to-Processor) 1-port cable (effectively a Twinax cable).


skylake sp with hfi to carrier.png


Regardless of the model, the integrated fabric die has a TDP of 8 Watts (note that this value is already included in the model's TDP value).

Sockets/Platform[edit]

Both Skylake X and PS are a two-chip solution linked together via Intel's standard DMI 3.0 bus interface which utilizes 4 PCIe 3.0 lanes (having a transfer rate of 8 GT/s per lane). Skylake SP has additional SMP capabilities which utilizes either 2 or 3 (depending on the model) Ultra Path Interconnect (UPI) links.

Core Socket Permanent Platform Chipset Chipset Bus SMP Interconnect
skylake x (back).png Skylake X LGA-2066 No 2-chip Lewisburg DMI 3.0
  Skylake SP LGA-3647 2-chip + 2-8-way SMP UPI

Packages[edit]

Core Die Type Package Dimensions
Skylake SP LCC FCLGA-3647 76.16 mm x 56.6 mm
HCC
XCC
Skylake X LCC FCLGA-2066 58.5 mm x 51 mm
HCC

Die[edit]

See also: Client Skylake's Die
Skylake SP chips and wafer.

Skylake Server class models and high-end desktop (HEDT) consist of 3 different dies: Low Core Count (LCC), High Core Count (HCC), and Extreme Core Count (XCC).

Low Core Count (LCC)[edit]

High Core Count (HCC)[edit]

Die shot of the octadeca core HEDT Skylake X processors.


skylake (octadeca core).png
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


skylake (octadeca core) (annotated).png

Extreme Core Count (XCC)[edit]

skylake-sp hcc die shot.png


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


skylake-sp hcc die shot (annotated).png

All Skylake Chips[edit]

 List of Skylake Processors
 Main processorFrequency/TurboMemMajor Feature Diff
ModelLaunchedPriceFamilyCore NameCoresThreadsL2$L3$TDPFrequencyMax TurboMax MemTurboSMT
 Uniprocessors
i7-7800X26 June 2017$ 389.00
€ 350.10
£ 315.09
¥ 40,195.37
Core i7Skylake X6126 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
i7-7820X26 June 2017$ 599.00
€ 539.10
£ 485.19
¥ 61,894.67
Core i7Skylake X8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
i9-7900X26 June 2017$ 999.00
€ 899.10
£ 809.19
¥ 103,226.67
Core i9Skylake X102010 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
i9-7920X28 August 2017$ 1,199.00
€ 1,079.10
£ 971.19
¥ 123,892.67
Core i9Skylake X122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
i9-7940X25 September 2017$ 1,399.00
€ 1,259.10
£ 1,133.19
¥ 144,558.67
Core i9Skylake X142814 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
3.1 GHz
3,100 MHz
3,100,000 kHz
4.3 GHz
4,300 MHz
4,300,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
i9-7960X25 September 2017$ 1,699.00
€ 1,529.10
£ 1,376.19
¥ 175,557.67
Core i9Skylake X163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
i9-7980XE25 September 2017$ 1,999.00
€ 1,799.10
£ 1,619.19
¥ 206,556.67
Core i9Skylake X183618 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
 Multiprocessors (2-way)
310411 July 2017$ 213.00
€ 191.70
£ 172.53
¥ 22,009.29
Xeon BronzeSkylake SP666 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
1.7 GHz
1,700 MHz
1,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
310611 July 2017$ 306.00
€ 275.40
£ 247.86
¥ 31,618.98
Xeon BronzeSkylake SP888 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
1.7 GHz
1,700 MHz
1,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
410811 July 2017$ 417.00
€ 375.30
£ 337.77
¥ 43,088.61
Xeon SilverSkylake SP8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
1.8 GHz
1,800 MHz
1,800,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
4109T11 July 2017$ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
Xeon SilverSkylake SP8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
70 W
70,000 mW
0.0939 hp
0.07 kW
2 GHz
2,000 MHz
2,000,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
411011 July 2017$ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
Xeon SilverSkylake SP8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
411211 July 2017$ 473.00
€ 425.70
£ 383.13
¥ 48,875.09
Xeon SilverSkylake SP484 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
411411 July 2017$ 694.00
€ 624.60
£ 562.14
¥ 71,711.02
Xeon SilverSkylake SP102010 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
4114T11 July 2017Xeon SilverSkylake SP102010 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
411611 July 2017$ 1,002.00
€ 901.80
£ 811.62
¥ 103,536.66
Xeon SilverSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
4116T11 July 2017Xeon SilverSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
 Multiprocessors (4-way)
511511 July 2017$ 1,221.00
€ 1,098.90
£ 989.01
¥ 126,165.93
Xeon GoldSkylake SP102010 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
511711 July 2017Xeon GoldSkylake SP142814 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
105 W
105,000 mW
0.141 hp
0.105 kW
2 GHz
2,000 MHz
2,000,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
5117F11 July 2017Xeon GoldSkylake SP142814 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
113 W
113,000 mW
0.152 hp
0.113 kW
2 GHz
2,000 MHz
2,000,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
511811 July 2017$ 1,273.00
€ 1,145.70
£ 1,031.13
¥ 131,539.09
Xeon GoldSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
105 W
105,000 mW
0.141 hp
0.105 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
5119T11 July 2017Xeon GoldSkylake SP142814 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
512011 July 2017$ 1,555.00
€ 1,399.50
£ 1,259.55
¥ 160,678.15
Xeon GoldSkylake SP142814 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
105 W
105,000 mW
0.141 hp
0.105 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
5120T11 July 2017$ 1,727.00
€ 1,554.30
£ 1,398.87
¥ 178,450.91
Xeon GoldSkylake SP142814 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
105 W
105,000 mW
0.141 hp
0.105 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
512211 July 2017$ 1,221.00
€ 1,098.90
£ 989.01
¥ 126,165.93
Xeon GoldSkylake SP484 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
105 W
105,000 mW
0.141 hp
0.105 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
612611 July 2017$ 1,776.00
€ 1,598.40
£ 1,438.56
¥ 183,514.08
Xeon GoldSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6126F11 July 2017$ 1,931.00
€ 1,737.90
£ 1,564.11
¥ 199,530.23
Xeon GoldSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
135 W
135,000 mW
0.181 hp
0.135 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6126T11 July 2017$ 1,865.00
€ 1,678.50
£ 1,510.65
¥ 192,710.45
Xeon GoldSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
612811 July 2017$ 1,697.00
€ 1,527.30
£ 1,374.57
¥ 175,351.01
Xeon GoldSkylake SP6126 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
115 W
115,000 mW
0.154 hp
0.115 kW
3.4 GHz
3,400 MHz
3,400,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
613011 July 2017$ 1,894.00
€ 1,704.60
£ 1,534.14
¥ 195,707.02
Xeon GoldSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6130F11 July 2017$ 2,049.00
€ 1,844.10
£ 1,659.69
¥ 211,723.17
Xeon GoldSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
135 W
135,000 mW
0.181 hp
0.135 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6130T11 July 2017$ 1,988.00
€ 1,789.20
£ 1,610.28
¥ 205,420.04
Xeon GoldSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
613211 July 2017$ 2,111.00
€ 1,899.90
£ 1,709.91
¥ 218,129.63
Xeon GoldSkylake SP142414 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
613411 July 2017$ 2,214.00
€ 1,992.60
£ 1,793.34
¥ 228,772.62
Xeon GoldSkylake SP8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
130 W
130,000 mW
0.174 hp
0.13 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6134M11 July 2017$ 5,217.00
€ 4,695.30
£ 4,225.77
¥ 539,072.61
Xeon GoldSkylake SP8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
130 W
130,000 mW
0.174 hp
0.13 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
613611 July 2017$ 2,460.00
€ 2,214.00
£ 1,992.60
¥ 254,191.80
Xeon GoldSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
3 GHz
3,000 MHz
3,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
613811 July 2017$ 2,612.00
€ 2,350.80
£ 2,115.72
¥ 269,897.96
Xeon GoldSkylake SP204020 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2 GHz
2,000 MHz
2,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6138F11 July 2017$ 2,767.00
€ 2,490.30
£ 2,241.27
¥ 285,914.11
Xeon GoldSkylake SP204020 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
135 W
135,000 mW
0.181 hp
0.135 kW
2 GHz
2,000 MHz
2,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6138T11 July 2017$ 2,742.00
€ 2,467.80
£ 2,221.02
¥ 283,330.86
Xeon GoldSkylake SP204020 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2 GHz
2,000 MHz
2,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
614011 July 2017$ 2,445.00
€ 2,200.50
£ 1,980.45
¥ 252,641.85
Xeon GoldSkylake SP183618 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6140M11 July 2017$ 5,448.00
€ 4,903.20
£ 4,412.88
¥ 562,941.84
Xeon GoldSkylake SP183618 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
614211 July 2017$ 2,946.00
€ 2,651.40
£ 2,386.26
¥ 304,410.18
Xeon GoldSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6142F11 July 2017$ 3,101.00
€ 2,790.90
£ 2,511.81
¥ 320,426.33
Xeon GoldSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
160 W
160,000 mW
0.215 hp
0.16 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6142M11 July 2017$ 5,949.00
€ 5,354.10
£ 4,818.69
¥ 614,710.17
Xeon GoldSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
614411 July 2017$ 2,925.00
€ 2,632.50
£ 2,369.25
¥ 302,240.25
Xeon GoldSkylake SP8168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
614611 July 2017$ 3,286.00
€ 2,957.40
£ 2,661.66
¥ 339,542.38
Xeon GoldSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
614811 July 2017$ 3,072.00
€ 2,764.80
£ 2,488.32
¥ 317,429.76
Xeon GoldSkylake SP204020 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6148F11 July 2017$ 3,227.00
€ 2,904.30
£ 2,613.87
¥ 333,445.91
Xeon GoldSkylake SP204020 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
160 W
160,000 mW
0.215 hp
0.16 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
615011 July 2017$ 3,358.00
€ 3,022.20
£ 2,719.98
¥ 346,982.14
Xeon GoldSkylake SP183618 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
615211 July 2017$ 3,655.00
€ 3,289.50
£ 2,960.55
¥ 377,671.15
Xeon GoldSkylake SP224422 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
30.25 MiB
30,976 KiB
31,719,424 B
0.0295 GiB
140 W
140,000 mW
0.188 hp
0.14 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
615411 July 2017$ 3,543.00
€ 3,188.70
£ 2,869.83
¥ 366,098.19
Xeon GoldSkylake SP183618 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
200 W
200,000 mW
0.268 hp
0.2 kW
3 GHz
3,000 MHz
3,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
6161Xeon GoldSkylake SP224422 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
30.25 MiB
30,976 KiB
31,719,424 B
0.0295 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
 Multiprocessors (8-way)
815311 July 2017$ 3,115.00
€ 2,803.50
£ 2,523.15
¥ 321,872.95
Xeon PlatinumSkylake SP163216 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
125 W
125,000 mW
0.168 hp
0.125 kW
2 GHz
2,000 MHz
2,000,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
815611 July 2017$ 7,007.00
€ 6,306.30
£ 5,675.67
¥ 724,033.31
Xeon PlatinumSkylake SP484 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
105 W
105,000 mW
0.141 hp
0.105 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
815811 July 2017$ 7,007.00
€ 6,306.30
£ 5,675.67
¥ 724,033.31
Xeon PlatinumSkylake SP122412 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
3 GHz
3,000 MHz
3,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
816011 July 2017$ 4,702.00
€ 4,231.80
£ 3,808.62
¥ 485,857.66
Xeon PlatinumSkylake SP244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8160F11 July 2017$ 4,856.00
€ 4,370.40
£ 3,933.36
¥ 501,770.48
Xeon PlatinumSkylake SP244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
160 W
160,000 mW
0.215 hp
0.16 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8160M11 July 2017$ 7,704.00
€ 6,933.60
£ 6,240.24
¥ 796,054.32
Xeon PlatinumSkylake SP244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
8160T11 July 2017$ 4,936.00
€ 4,442.40
£ 3,998.16
¥ 510,036.88
Xeon PlatinumSkylake SP244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
816411 July 2017$ 6,114.00
€ 5,502.60
£ 4,952.34
¥ 631,759.62
Xeon PlatinumSkylake SP265226 MiB
26,624 KiB
27,262,976 B
0.0254 GiB
35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
150 W
150,000 mW
0.201 hp
0.15 kW
2 GHz
2,000 MHz
2,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
816811 July 2017$ 5,890.00
€ 5,301.00
£ 4,770.90
¥ 608,613.70
Xeon PlatinumSkylake SP244824 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
205 W
205,000 mW
0.275 hp
0.205 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
817011 July 2017$ 7,405.00
€ 6,664.50
£ 5,998.05
¥ 765,158.65
Xeon PlatinumSkylake SP265226 MiB
26,624 KiB
27,262,976 B
0.0254 GiB
35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8170FXeon PlatinumSkylake SP265226 MiB
26,624 KiB
27,262,976 B
0.0254 GiB
35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8170M11 July 2017$ 10,409.00
€ 9,368.10
£ 8,431.29
¥ 1,075,561.97
Xeon PlatinumSkylake SP265226 MiB
26,624 KiB
27,262,976 B
0.0254 GiB
35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
8173MXeon PlatinumSkylake SP285628 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
2.1 GHz
2,100 MHz
2,100,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
817611 July 2017$ 8,719.00
€ 7,847.10
£ 7,062.39
¥ 900,934.27
Xeon PlatinumSkylake SP285628 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8176F11 July 2017Xeon PlatinumSkylake SP285628 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
173 W
173,000 mW
0.232 hp
0.173 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8176M11 July 2017$ 11,722.00
€ 10,549.80
£ 9,494.82
¥ 1,211,234.26
Xeon PlatinumSkylake SP285628 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
165 W
165,000 mW
0.221 hp
0.165 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
818011 July 2017$ 10,009.00
€ 9,008.10
£ 8,107.29
¥ 1,034,229.97
Xeon PlatinumSkylake SP285628 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
205 W
205,000 mW
0.275 hp
0.205 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
768 GiB
786,432 MiB
805,306,368 KiB
824,633,720,832 B
0.75 TiB
8180M11 July 2017$ 13,011.00
€ 11,709.90
£ 10,538.91
¥ 1,344,426.63
Xeon PlatinumSkylake SP285628 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
205 W
205,000 mW
0.275 hp
0.205 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
1,536 GiB
1,572,864 MiB
1,610,612,736 KiB
1,649,267,441,664 B
1.5 TiB
Count: 70

References[edit]

  • Intel Unveils Powerful Intel Xeon Scalable Processors, Live Event, July 11, 2017

Documents[edit]

codenameSkylake (server) +
core count4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 + and 28 +
designerIntel +
first launchedMay 4, 2017 +
full page nameintel/microarchitectures/skylake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-16 +, x86-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameSkylake (server) +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +