| nMOS/pMOS || depletion-mode nMOS || nMOS/pMOS/CMOS ||

| HMOS-II || HMOS-E || P646 (CHMOS III) || NMOS III || || CMOS-2 ! colspan="3" | [[HP]] NMOS-III Design Rules

| nMOS || CMOS || CMOS || BiCMOS

| tech = nMOS ...designed by [[Toshiba]] during the late 1970s. The [[microprocessor]] uses nMOS technology and was primarily used in printers and displays.

...d became the first truly widely used DRAM chip. Those chips used Si-gate [[nMOS]] transistors using a polysilicon word line and an aluminum metal bit line. | fab 1 xtor.tech = nMOS, pMOS

* pull-down network (PDN) - a set of [[NMOS]] transistors connected between GND and the output line

[[File:Nmos.svg|thumb|right|[[n-type semiconductor]].]] An '''nMOS transistor''' is built with a p-type body with two regions of n-type semico

...to HIGH as it's connected to VDD but not GND. When the input is HIGH, the nMOS transistor is on and the pMOS transistor is off yielding an output that is ...e \( i_{DP} = i_{DN} = 0 \). When the input is LOW, pMOS is conducting and nMOS is off; the load capacitor is charged via the pMOS device.The power dissipa

| tech = nMOS

| tech = nMOS

| tech 2 = nMOS ...instructions with a 10 microsecond instruction cycle. The chips come in [[nMOS]], [[pMOS]], and [[CMOS]] versions.

| tech 2 = nMOS | {{matsushita|MN1542}} || 2048x8 ROM, 152x4 RAM, 28 I/O || NMOS ||

...]], the 10800 series was designed for very high speed applications where [[nMOS]] components were insufficient.

.... A year later, National introduced the {{national|cops ii|COPS II}}, an [[nMOS]] (and later [[CMOS]]) versions of those chips.

| tech = nMOS ...national|cops i|COPS I}} in 1977. Components in the COPS II were made in [[nMOS]] and [[CMOS]] technology instead of [[pMOS]] as used in COPS I. The COPS I

| {{\|3222}} || Refresh Controller for 4K NMOS DRAMs

| tech = nMOS ...40/MB8840H series''' is a [[microprocessor family|family]] of {{arch|4}} [[nMOS]] [[microcontroller]]s developed by [[Fujitsu]] and introduced in 1977{{dat

* {{fujitsu|MB8840}}, a [[NMOS]] version

...is architecturally identical to the {{fujitsu|MB8840|MB8840 family}} (An [[nMOS]] version). The {{fujitsu|MB88500}} series is a high-speed version of this * {{fujitsu|MB8840}}, a [[NMOS]] version

| tech = nMOS

...fet|MOS]] [[transistor]]s - [[pmos transistor|pMOS]] and [[pMOS transistor|nMOS]]. CMOS is the dominant technology used for [[VLSI]] and [[ULSI]] circuit ...S]] and [[nMOS transistor|nMOS]]. To better understand this, consider an [[nMOS transistor]]. Because it can pull no higher than V_DD - V<sub>t</

...ors are cascaded with an [[NPN transistor]]. When the input is HIGH, the [[NMOS transitor]] is conducting becoming the base current for the Q₂ N

...removing redundant sets of [[pMOS transistor|pMOS]] and [[nMOS transistor|nMOS]] pairs of [[transistor]]s.

*** [[nmos logic|n-type metal–oxide–semiconductor logic]] (nMOS)

| tech 2 = nMOS ...OS logic|pMOS]] technology, TI later expended the family into [[nMOS logic|nMOS]] and [[CMOS]].

| tech = nMOS

| tech = nMOS ...1975. The chipset was manufactured by [[Western Digital]] in [[nMOS logic|nMOS]] technology under a $6.3M contract<ref>{{apa mag|month=February|day=26|yea

| tech = nMOS

| tech = nMOS

| tech = nMOS

| tech = nMOS

| tech = nMOS ...designed by [[Toshiba]] during the late 1970s. The [[microprocessor]] uses nMOS technology and was primarily used in very low-end controllers.

| tech = nMOS

| tech = nMOS

| tech = nMOS

...[[Intel]]'s 2nd generation FinFET transistors. Intel uses TiN pMOS / TiAlN nMOS as work function metals. Intel makes use of 193 nm immersion lithography wi ...irst generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Samsung node has gone through a number of refineme

[[File:intel 14nm+ (nmos).png|400px]]

| NMOS I | nMOS

...ng density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]. While they succeeded in doubling the den | fab 1 xtor.tech = nMOS

| nMOS || nMOS || nMOS

** [[Allows value::nMOS]]

| tech = nMOS

...d. These chips were remade by AMD in [[static CMOS]] design (as opposed to nMOS), resulting in considerably lower power dissipation. This MPU was rated to

...d. These chips were remade by AMD in [[static CMOS]] design (as opposed to nMOS), resulting in considerably lower power dissipation. This MPU was rated to

...d. These chips were remade by AMD in [[static CMOS]] design (as opposed to nMOS), resulting in considerably lower power dissipation. This MPU was rated to

...d. These chips were remade by AMD in [[static CMOS]] design (as opposed to nMOS), resulting in considerably lower power dissipation. This MPU was rated to

...d. These chips were remade by AMD in [[static CMOS]] design (as opposed to nMOS), resulting in considerably lower power dissipation. This MPU was rated to

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| tech = nMOS ...instance of::microprocessor]][[microprocessor family::Am186]][[technology::nMOS]]

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| tech = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

[[File:intel 14nm++ (nmos).png|400px]]

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = nMOS

| technology = <!-- technology (e.g. CMOS, pMOS, nMOS, etc..) -->

| technology = nMOS * [[nMOS]] transistors

...[PLA]]s. Layout was generated automatically using EDA tools using [[Psuedo nMOS]] logic in order to save on space, albeit at the slight expense of static p

...ecouples the read port from the write port. A new read buffer comprising 2 nMOS transistors is added to the 6T cell.

Typically, the area between the end of the nMOS and pMOS devices is used as the gate contact hit location. In an effort to

...gate region, thereby reducing the dead space region between the end of the nMOS and the end of the pMOS devices. Traditionally, the gate is extended from the nMOS/pMOS device outward over the inactive isolation region. The gate via is the