...e}} || KBL-H || || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations ...ore}} || KBL-S || || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis

...}} (A) and later {{\|Am2045B}} had over 300 cores with maximum theoretical performance of over one trillion operations per second. Due to the [[wikipedia:2008 fin * 2x '''Compute Units''' (CU)

...e of covering the entire computing spectrum from fanless notebooks to high-performance desktop computers. Zen was officially launched on March 2, [[2017]]. Zen wa For performance desktop and mobile computing, Zen is branded as {{amd|Athlon}}, {{amd|Ryzen

For performance desktop and mobile computing, Zen is branded as {{amd|Athlon}}, {{amd|Ryzen ...amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|some}} ||

...s support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache. == Performance ==

...s support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache. == Performance ==

POWER9-based microprocessors are fabricated on [[GlobalFoundries]]'s High-Performance [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) pr * Higher single-thread performance

...decc|VAX 11/780}}, the prototypes ended up achieveing between 2x to 4x the performance of the [[DEC]] {{decc|VAX 11/780}}; this is roughly equivalent to 10 times * Goal 1.5x performance of the {{decc|VAX 11/780}}

| {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]] for the Core Compute Die (CCD), the same process used in Zen 2 Refresh processors, as well as [[

...troduced by [[Intel]] in 2017. The Xeon Platinum series offers the highest performance, highest scalability, and highest flexibility. ...n E7}} and the {{\\|Xeon E5}} families. Xeon Platinum provides the highest performance and flexibility out of all the Xeon families, thus placing it above the {{\

...lining]] technique in order to improve performance and efficiency. At peak performance the ARM2 can reach 10 [[million instructions per second]] with an average o ...ddress translation is necessary and prepare ahead. This is done to improve performance because it can make use of [[Page-Mode DRAM]], allowing for more efficient

...ction of execution resources due to die size or complexity constraints, or performance optimizations where execution resources are dynamically disabled if power o ...de>{{link|#SQRT}}</code> and <code>{{link|#DIV}}</code> instructions which compute full precision results. Also <code>RSQRT</code> and <code>{{link|#RCP}}</co

! rowspan="2" | Name !! rowspan="2" | Compute Units !! rowspan="2" | Shaders!! colspan="2" | [[Vulkan]] !! colspan="3" | ! rowspan="2" | Name !! rowspan="2" | Compute Units !! rowspan="2" | Shaders!! colspan="2" | [[Vulkan]] !! colspan="3" |

...he ''Scorpio Engine'' most important goal was achieving true [[4K]] gaming performance according to John Sell, a Distinguished Engineer at Microsoft who presented ...ev kit can deliver a reported 6.6 TFLOPS with its four additional CUs. The performance of texture processing has also been increased to 187.5 G bilinear [[texels]

...ecute [[machine learning]] algorithms. NPUs are designed to accelerate the performance of common machine learning tasks such as image classification, machine tran ...ng are designed to accelerate the curating of new models. This is a highly compute-intensive operation that involves inputting an existing dataset (typically

...l [[2015]], Aurora was planned to be delivered in [[2018]] and have a peak performance of 180 [[petaFLOPS]]. The system was expected to be the world's most powerf | Compute Nodes || >50,000

Announced in September 2017, Loihi is predominantly a research chip meaning performance characteristics are not guaranteed. This is Intel's 5th chip in the neuromo ...arch, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing").

* 3x-4x+ performance ...or a total of 98,304 [[FLOPs]] each cycle for a total of up to 119 TOPS of compute. The MPUs are fed by 60 MiB of distributed SRAM. Spring Crest uses [[bfloat

'''Kaby Lake G''' ('''KBL-G''') is the name of the core for [[Intel]]'s high-performance line of mobile processors based on the {{intel|Kaby Lake|l=arch}} microarch ***** 24 Compute Units

...[SMT]] and a {{amd|Vega|l=arch}} integrated graphics processor with 6 or 7 compute units in {{amd|FP6|package FP6|l=package}}.

...[[convolutional neural network]]s (CNN). The GAP8 is said to offer a peak performance of up to 200 MOPS at 1 mW and up to 10 GOPS at a few tens of mW, making it ...the rest of the system is in deep idle state. The microcontroller and the compute engines sit on two entirely decoupled power domains, consuming power sparin

...ic processor]] designed from the ground-up in order to deliver the highest performance at low power. ...relies equally on both hardware and software in order to achieve the high performance and efficiency by using TensorFlow for machine learning and Halide for imag

'''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server ...ased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel).

...educed the number of nodes to only 4,608, but tenfold the peak theoretical performance from 27 petaFLOPS to around 225 PF. Summit has over 200 [[petaFLOPS]] of theoretical compute power and over 3 AI exaFLOPS for AI workloads.

...16 GT/s and 25 GT/s per link with support for port aggregation for higher performance. ...te-Architectures-Availability ''CCIX™ Consortium Enables Next Generation Compute Architectures with the Availability of Base Specification 1.0''] [Press rel

=== High-performance === ...roprocessor models by bitmain]] [[family::Sophon]] [[market segment::!Edge Compute]]

...AMD]] for the first three generations of their {{amd|EPYC}} family of high performance server processors. It supports eight channels of [[DDR4]] memory and eight ...layout, and schematic were published by the [https://opencompute.org Open Compute Project] under Project Olympus AMD EPYC, specifically the US1-EPYC implemen

...his chip can deliver 3.994 [[TFLOPS]] raw peak performance - about 66% the performance of the {{microsoft|Scorpio Engine}} (6 TFLOPS) and three times its predeces <tr><th>Peak Performance</th><td> ~4 TFLOPS (3,994,000,000,000 [[FLOPS]])</td></tr>

...rgy]] as part of a program that evaluates the feasibility of emerging high-performance computing architectures as production platforms to support NNSA's mission. ...CN9975]] processors with slightly over 1.2 MW power consumption for a peak performance of 2.322 [[petaFLOPS]]. Each [[ThunderX2 CN9975]] has [[28 cores]] operatin

'''Neoverse N1''' (codename '''Ares''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server m ..., the Neoverse N1 is said to deliver a significant uplift in single-thread performance.

...ing-point operations per second''' ('''FLOPS''') is a measure of [[compute performance]] used to quantify the number of [[floating-point]] [[floating-point operat ...ing]] (e.g., [[supercomputers]]) in order to evaluate the peak theoretical performance of various scientific workloads. Traditionally, the FLOPS of a microprocess

...t data graph execution]] architecture designed by [[Intel]] for the [[high-performance computing]] and [[data center]] markets. The CSA is designed to work alongs ...ng the traditional [[out-of-order]] [[superscalar]] while surpassing it in performance and power. CSA supports the same HPC programming models supported by tradit

.../1100/offering-unmatched-performance-leadership-energy "Offering Unmatched Performance, Leadership Energy Efficiency and Next-Generation Architecture, AMD Brings ...6 interfaces can be configured as cache-coherent {{wp|Compute Express Link|Compute Express Link}}. "Genoa" supports version 1.1 of the protocol, specifically

...successor to the {{\\|SX-ACE}}, a [[vector processor]] designed for [[high-performance]] scientific/research applications and supercomputers. The SX-Aurora deviat ...engine but a self-hosted accelerator, the SPU is designed to deliver high performance to keep pace with the VPU and other operating system-related tasks.

...mmon [[figure of merit]] in the [[HPC]] community used to analyze the peak performance of a system under [[memory-bound]] workloads.

...5 Silver]] high-efficiency cores operating at 1.8 GHz along with four high-performance [[Kryo 495 Gold]] operating at 2.84 GHz. The Snapdragon 8cx integrates the [[File:snapdragon-8cx-compute-platform-chip-on-wafer.jpg|thumb|right]]

'''Exynos 9820''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early ...ACs split between two execution cores. The new NPU is capable of a peaking compute of two teraOPS.

|market=Edge Compute ...chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumpt

'''Xeon Platinum 9282''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

'''Xeon Platinum 9242''' is a [[48-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

'''Xeon Platinum 9222''' is a [[32-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

'''Xeon Platinum 9221''' is a [[32-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 92 ...not be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

...and [[OCP OAM|OAM]] form factors that have high TDPs designed for maximum performance at the data center and for workstations. Unlike the NNP-T, NNP-I inference ...ormance uplift. Intel claims that these chips have about 3-4x the training performance of first generation. All NNP-T 1000 chips come with 32 GiB of four [[HBM2]]

'''TaiShan v110''' is the successor to the {{\\|TaiShan v100}}, a high-performance [[ARM]] server microarchitecture designed by [[HiSilicon]] for [[Huawei]]'s ...ormance [[ARM]] core and SoC design. The chip, which incorporates multiple compute dies and an I/O is a multi-chip package, is fabricated on [[TSMC]]'s [[7 nm

'''Lakefield''' ('''LKF''') is a high-performance low-power [[3d integrated circuit|3D]] microarchitecture designed by Intel ** [[10 nm]] compute field

...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui

...ased on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui

...ased on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui

...ased on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on ...Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circui

** 12 inference and compute units (ICEs) *** DL compute grid

<tr><th>Peak Performance</th><td>2.551 [[petaFLOPS]] (DP)</td></tr> ...erlink all the nodes. ARCHER uses a [[Dragonfly topology]]. There are four compute nodes connected per each Aries router, 188 nodes per cabinet, and two cabin

...e planned successor to {{\\|ARCHER}} intended to deliver an average of 11x performance improvement over its predecessor. The system is based on [[Cray]] Shasta an <tr><th>Peak Performance</th><td>26.35 petaFLOPS</td></tr>

...oyed in a number of phases with each phase upgrading it to over double the performance. ! Cores || Peak Compute

'''Exynos 990''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in [[202 ...new NPU features two execution cores. The new NPU is capable of a peaking compute of fifteen trillion operations per second (TOPs).

...rket. Fabricated on TSMC [[16 nm process]], the chip integrates eight high-performance [[x86]] "CNS" cores along with a brand new clean-sheet design "NCORE" [[neu ...ores also introduce the {{x86|AVX-512}} extension in order to offer better performance, flexibility, and offer better ISA compatibility with other [[x86]] vendors

...pring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} enabled for a peak performance of 170 [[TOPS]] at a TDP of 75 W. == Peak Performance ==

...{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} for a peak performance of 50 [[TOPS]] at a TDP of 12 W. This chip comes in an [[M.2]] [[accelerato == Peak Performance ==

==== Compute Engine ==== :[[File:mlp compute engine block diagram.svg|550px]]

...e through various configurations based on the SRAM sizes and the number of compute engines. ...rm's {{armh|CCN-500}} or {{armh|CMN-600}} interconnects to scale to higher performance. For example, eight of the {{armh|Ethos-N77|l=core}} can be integrated toge

...:File:AMD-K5 Processor Performance Brief (June, 1996).pdf|AMD-K5 Processor Performance Brief]]||1996-06|| ...7.pdf White Paper: Next Generation Connectivity Solutions: AMD’s Managed Performance Portfolio]||1998-03||

{{eta compute title|ECM3532}} |designer=Eta Compute

...EA-Leti]] demonstarting the theoretical capabilities of a large-scale high-performance 3D stacked [[chiplets]]-based SoC technology. The project comprised 96 [[MI ** 6 compute [[chiplets]]

...[[AMD]] [[amd/opteron|Opteron]] 6000 Series microprocessors optimized for performance per Watt and scalability. The designation G34 stands for AMD's third genera ...the {{amd|K10|l=arch}} microarchitecture, and Family 15h featuring up to 8 compute units (not exactly 16 cores) based on the {{amd|Bulldozer|l=arch}} and {{am

...h}}) in {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance. ...The Cortex-A510 is also designed to seamlessly integrate along with higher-performance cores through [[Arm]]'s {{armh|DynamIQ big.LITTLE}} technology.

...h generation of their {{amd|EPYC#7004 Series (Zen 4)|EPYC}} family of high performance server processors, succeeding {{\\|Socket SP3}}. Its counterpart for deskto Compute Express Links enable cache coherent links to peripheral devices. Type-0 pro