Semiconductor & Computer Engineering
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Difference between revisions of "64-bit architecture"
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* {{ibm|POWER9}} | * {{ibm|POWER9}} | ||
}} | }} | ||
| + | </div> | ||
| + | |||
| + | === [[SPARC]] === | ||
| + | <div style="margin: 30px;"> | ||
| + | '''Fujitsu''' | ||
| + | * {{fujitsu|SPARC64}} | ||
| + | '''Oracle''' | ||
| + | * {{oracle|SPARC}} | ||
| + | '''Sun Microsystems''' | ||
| + | * {{sun|UltraSPARC}} | ||
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=== Other === | === Other === | ||
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| − | + | '''NEC SX''' | |
| + | * [[nec/microarchitectures/sx-aurora|SX-Aurora]] | ||
</div> | </div> | ||
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=== Research/University === | === Research/University === | ||
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Latest revision as of 02:48, 17 March 2019
The 64-bit architecture is a microprocessor or computer architecture that has a datapath width or a highest operand width of 64 bits or 8 octets. These architectures typically have a matching register file with registers width of 64 bits.
Contents
64-bit microprocessors[edit]
Alpha[edit]
DEC
ARM[edit]
MIPS[edit]
Cavium
POWER[edit]
SPARC[edit]
x86[edit]
AMD
Intel
- NetBurst
- Core
- Penryn
- Bonnell
- Nehalem
- Westmere
- Sandy Bridge (client)
- Saltwell
- Ivy Bridge
- Silvermont
- Haswell
- Broadwell
- Airmont
- Skylake (client)
- Kaby Lake
- Goldmont
- Skylake (server)
- Coffee Lake
- Goldmont Plus
- Knights Mill
- Palm Cove
- Whiskey Lake
- Amber Lake
- Cannon Lake
- Tremont
- Cascade Lake
- Snow Ridge
- Sunny Cove
- Lakefield
- Ice Lake (client)
- Willow Cove
- Cooper Lake
- Tiger Lake
- Gracemont
- Alder Lake
- Rocket Lake
- Ice Lake (server)
- Golden Cove
- Ocean Cove
- Raptor Lake
- Sapphire Rapids
- Meteor Lake
- Emerald Rapids
- Granite Rapids
- Sierra Forest
- Diamond Rapids
IA-64[edit]
Other[edit]
NEC SX
Research/University[edit]
- Princeton
This list is incomplete; you can help by expanding it.
64-bit microcontrollers[edit]
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