Revision as of 21:30, 31 March 2019

Intel Xeon D
Xeon D
Developer	Intel
Manufacturer	Intel
Type	System in packages
Introduction	March 9, 2015 (announced) March 9, 2015 (launch)
ISA	x86-64
µarch	Broadwell, Skylake (server)
Word size	64 bit 8 octets 16 nibbles
Process	14 nm 0.014 μm 1.4e-5 mm
Technology	CMOS
Clock	1300 MHz-2400 MHz
Package	fcBGA-1667
Socket	BGA-1667

Xeon D is a family of 64-bit multi-core x86 microserver single-chip processors introduced by Intel in March of 2015. Xeon D chips are aimed at filling the gap between the Atom and the Xeon E3 families. Targeting the low-end server market, the Xeon D family puts priority on efficiency and networking - areas where dense, lower-power, lightweight hyperscale workloads are expected.

History

The Xeon D began as a joint collaboration between Facebook and Intel in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The design calls for dense nodes of lower power but highly concurrent workload which tends to be mostly memory-bandwidth-bound. While early designs where mostly based on the Atom SoCs, their performance proved to be too much of a bottleneck on its own. Xeon D is a middle-tier family that's a step above Atom in terms of performance, but below Xeon E3 power-wise. Xeon D is largely driven by high concurrency and better memory capabilities.

Currently, Intel offers two series of Xeon D parts - dense low-power and dense high-power parts.

Dense Low-Power

D-1500 Series (Broadwell)

Main articles: Broadwell (Server) µarch and Broadwell DE Core

First-generation of dense low-power Xeon D parts were introduced in early 2015 and are based on the Broadwell microarchitecture. Fabricated on their 14 nm process, those parts incorporate up to sixteen cores with a TDP of up to 65 W.

• TDP: 20-65 W
• Mem: 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ RDIMM 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM
• I/O: 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2)
• ISA: Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2)
• Features: SpeedStep, VT-x, TSX, TXT, Secure Key, and OS Guard

All models are a single-chip solution, meaning both the CPU die and the chipset die are packaged together on the same substrate.

Hewitt Lake

Main article: Hewitt Lake core

Announced in February 2019, Hewitt Lake will be next-generation Xeon D processors.

Dense High-Power

D-2100 Series (Skylake)

Main articles: Skylake (server) Microarchitecture and Skylake DE core

Introduced in February 2018, Xeon D-2100 series processors are based on the Skylake microarchitecture. Those low-power variant range from 4 to 18 cores with hyperthreading support. As with the previous generations, those chips are also a single-chip solution - the Lewisburg chipset is incorporated into the same package as the processor. Being based on the new Skylake microarchitecture means those parts are also based on the mesh architecture which brought a much bigger L2 cache and supports twice as many memory channels. Additionally, all models also support AVX-512 with a single execution unit.

SKUs are suffixed with either I, T, and N or combination of multiple of those options:

• I - Integrated Ethernet
• T - High Temperature (90° T_CASE) and extended reliability support
• N - Integrated Ethernet and Intel's QuickAssist technology

All models have all the following features in common:

• Mem: Up 512 GiB of quad-channel DDR4 Memory
  • DPC RDIMM and LRDIMM \w ECC
• I/O: 32 PCIe 3.0 Lanes + 20 configurable High-Speed I/O (HSIO) lanes
• TDP: < 110 W
• ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
• Features: Speed Shift, vPro, VT-x/EPT, VT-d, TBT 2.0, TSX, TXT, SpeedStep, Secure Key, MPX, OS Guard, and RAS.

See also

• Qualcomm Centriq