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Difference between revisions of "intel/microarchitectures/core (client)"
< intel‎ | microarchitectures

(→‎Overview)
(→‎Overview)
 
Line 31: Line 31:
 
=== Intel Core Lines ===
 
=== Intel Core Lines ===
 
{{see also|Intel|intel/atom}}
 
{{see also|Intel|intel/atom}}
−
{| class="wikitable mw-datatable" style="margin:0.2em auto; text-align:center; min-width:75em;"
+
{| class="wikitable mw-datatable" style="margin:0.2em auto; text-align:center; min-width:72em;"
 
|+Intel Core (+ Pentium 4) Roadmap
 
|+Intel Core (+ Pentium 4) Roadmap
 
|-
 
|-
Line 49: Line 49:
 
|-
 
|-
 
| [[180 nm]]
 
| [[180 nm]]
−
| rowspan="2" | [[NetBurst]]
+
! rowspan="2" | [[NetBurst]]
 
| {{intel|Willamette|l=core}}
 
| {{intel|Willamette|l=core}}
 
| colspan="2" rowspan="3" | &mdash;
 
| colspan="2" rowspan="3" | &mdash;
−
| 2000-11-20
+
| 2000-11
 
| &mdash;
 
| &mdash;
 
| {{intel|Willamette|l=core}}
 
| {{intel|Willamette|l=core}}
Line 61: Line 61:
 
| [[130 nm]]<hr>[[90 nm]]
 
| [[130 nm]]<hr>[[90 nm]]
 
| {{intel|Northwood|l=core}}<hr>{{intel|Prescott|l=arch}}
 
| {{intel|Northwood|l=core}}<hr>{{intel|Prescott|l=arch}}
−
| 2002-01-07
+
| 2002-01
 
| Northwood <br>Mobile
 
| Northwood <br>Mobile
 
| Northwood <hr>Prescott
 
| Northwood <hr>Prescott
Line 69: Line 69:
 
|- <!-- Pentium M (arch): Core: Banias, Dothan, Stealey, Canmore, Tolapai; Core: (Atom) Diamondville, Silverthorne -->
 
|- <!-- Pentium M (arch): Core: Banias, Dothan, Stealey, Canmore, Tolapai; Core: (Atom) Diamondville, Silverthorne -->
 
| [[130 nm]]<hr>[[90 nm]]<hr>[[90 nm]]<hr>[[65 nm]]
 
| [[130 nm]]<hr>[[90 nm]]<hr>[[90 nm]]<hr>[[65 nm]]
−
| {{intel|Pentium M|l=arch}}<br>.<hr>.<br>{{intel|Pentium D|l=arch}}<!-- Pentium D: 90 nm Smithfield, 65 nm Presler -->
+
! {{intel|Pentium M|l=arch}}<br>.<hr>.<br>{{intel|Pentium D|l=arch}}<!-- Pentium D: 90 nm Smithfield, 65 nm Presler -->
 
| {{intel|Banias|l=core}}<hr>{{intel|Dothan|l=core}}<hr>{{intel|Smithfield|l=core}}<hr>{{intel|Presler|l=core}}
 
| {{intel|Banias|l=core}}<hr>{{intel|Dothan|l=core}}<hr>{{intel|Smithfield|l=core}}<hr>{{intel|Presler|l=core}}
−
| 2004-02-01
+
| 2004-02
 
| {{intel|Banias|l=core}}<hr>{{intel|Dothan|l=core}}
 
| {{intel|Banias|l=core}}<hr>{{intel|Dothan|l=core}}
 
| {{intel|Smithfield|l=core}}<hr>{{intel|Presler|l=core}}
 
| {{intel|Smithfield|l=core}}<hr>{{intel|Presler|l=core}}
Line 79: Line 79:
 
|-
 
|-
 
| rowspan="2" | [[65 nm]]
 
| rowspan="2" | [[65 nm]]
−
| {{intel|Modified Pentium M|Modified <br>Pentium M|l=arch}}
+
! {{intel|Modified Pentium M|Modified <br>Pentium M|l=arch}}
 
| {{intel|Yonah|l=core}}<br>{{intel|Cedar Mill|l=core}}
 
| {{intel|Yonah|l=core}}<br>{{intel|Cedar Mill|l=core}}
−
| 1<br><small>(Yonah<br>only)</small>
+
| 1<br><small>(Yonah)</small>
 
| rowspan="10" | &mdash;
 
| rowspan="10" | &mdash;
−
| 2006-01-05
+
| 2006-01
 
| Yonah
 
| Yonah
 
| Cedar Mill
 
| Cedar Mill
 
| -
 
| -
 
| Dempsey<br>Sossaman
 
| Dempsey<br>Sossaman
−
| Xeon "Tulsa" <br>(65 nm)
+
| Tulsa <br>('''Xeon''')
 
|-
 
|-
−
| rowspan="2" | '''{{intel|core|Intel Core|l=arch}}'''
+
! rowspan="2" | '''{{intel|core|Intel Core|l=arch}}'''
 
| {{intel|Merom|l=core}}
 
| {{intel|Merom|l=core}}
 
| rowspan="2" | 2
 
| rowspan="2" | 2
−
| 2006-07-27
+
| 2006-07
 
| {{intel|Merom|l=core}}<br>Merom-L
 
| {{intel|Merom|l=core}}<br>Merom-L
 
| {{intel|Conroe|l=core}}
 
| {{intel|Conroe|l=core}}
Line 102: Line 102:
 
| rowspan="2" | [[45 nm]]
 
| rowspan="2" | [[45 nm]]
 
| [[Penryn]]
 
| [[Penryn]]
−
| 2007-11-11
+
| 2007-11
 
| {{intel|Penryn|l=arch}}
 
| {{intel|Penryn|l=arch}}
 
| {{intel|Wolfdale|l=core}}
 
| {{intel|Wolfdale|l=core}}
Line 109: Line 109:
 
| {{intel|Dunnington|l=core}}
 
| {{intel|Dunnington|l=core}}
 
|-
 
|-
−
| rowspan="2" | {{intel|Nehalem|l=arch}}
+
! rowspan="2" | {{intel|Nehalem|l=arch}}
 
| {{intel|Nehalem|l=arch}}
 
| {{intel|Nehalem|l=arch}}
 
| rowspan="2" | 1 <br>(Core i)
 
| rowspan="2" | 1 <br>(Core i)
−
| 2008-11-17
+
| 2008-11
 
| {{intel|Clarksfield|l=core}}
 
| {{intel|Clarksfield|l=core}}
 
| {{intel|Lynnfield|l=core}}
 
| {{intel|Lynnfield|l=core}}
Line 121: Line 121:
 
| rowspan="2" | [[32 nm]]
 
| rowspan="2" | [[32 nm]]
 
| {{intel|Westmere|l=arch}}
 
| {{intel|Westmere|l=arch}}
−
| 2010-01-04
+
| 2010-01
 
| {{intel|Arrandale|l=core}}
 
| {{intel|Arrandale|l=core}}
 
| {{intel|Clarkdale|l=core}}
 
| {{intel|Clarkdale|l=core}}
 
| {{intel|Gulftown|l=core}}
 
| {{intel|Gulftown|l=core}}
−
| Westmere-EP
+
| {{intel|Westmere EP|l=core}}
−
| Westmere-EX
+
| {{intel|Westmere EX|l=core}}
 
|-
 
|-
−
| rowspan="2" | {{intel|Sandy Bridge|l=arch}}
+
! rowspan="2" | {{intel|Sandy Bridge|l=arch}}
 
| {{intel|Sandy Bridge|l=arch}}
 
| {{intel|Sandy Bridge|l=arch}}
 
| 2
 
| 2
−
| 2011-01-09
+
| 2011-01
 
| {{intel|Sandy Bridge M|l=core}}
 
| {{intel|Sandy Bridge M|l=core}}
 
| {{intel|Sandy Bridge|l=arch}}
 
| {{intel|Sandy Bridge|l=arch}}
 
| {{intel|Sandy Bridge E|l=core}}
 
| {{intel|Sandy Bridge E|l=core}}
−
| Sandy Bridge-EP
+
| {{intel|Sandy Bridge EP|l=core}}
 
| &mdash;
 
| &mdash;
 
|-
 
|-
Line 141: Line 141:
 
| {{intel|Ivy Bridge|l=arch}}
 
| {{intel|Ivy Bridge|l=arch}}
 
| 3
 
| 3
−
| 2012-04-29
+
| 2012-04
 
| {{intel|Ivy Bridge M|l=core}}
 
| {{intel|Ivy Bridge M|l=core}}
 
| {{intel|Ivy Bridge|l=arch}}
 
| {{intel|Ivy Bridge|l=arch}}
 
| {{intel|Ivy Bridge E|l=core}}
 
| {{intel|Ivy Bridge E|l=core}}
−
| Ivy Bridge-EP
+
| {{intel|Ivy Bridge EP|l=core}}
−
| Ivy Bridge-EX
+
| {{intel|Ivy Bridge EX|l=core}}
 
|-
 
|-
−
| rowspan="2" | {{intel|Haswell|l=arch}}
+
! rowspan="2" | {{intel|Haswell|l=arch}}
 
| [[Haswell]]
 
| [[Haswell]]
 
| rowspan="2" | 4
 
| rowspan="2" | 4
−
| nobr|2013-06-0
+
| 2013-06
−
| Haswell-H<br>Haswell-MB<br>Haswell-ULP<br>Haswell-ULX
+
| {{intel|Haswell H|l=core}}<br>{{intel|Haswell MB|l=core}}<br>{{intel|Haswell ULP|l=core}}<br>{{intel|Haswell ULX|l=core}}
−
| Haswell-DT
+
| {{intel|Haswell DT|l=core}}
−
| Haswell-E
+
| {{intel|Haswell E|l=core}}
−
| Haswell-EP
+
| {{intel|Haswell EP|l=core}}
−
| Haswell-EX
+
| {{intel|Haswell EX|l=core}}
 
|-
 
|-
 
| ''Devil's Canyon''
 
| ''Devil's Canyon''
 
| 2014-06
 
| 2014-06
 
| &mdash;
 
| &mdash;
−
| Haswell-DT
+
| Haswell DT
 
| colspan=3 | &mdash;
 
| colspan=3 | &mdash;
 
|-
 
|-
 
| rowspan="10" | [[14 nm]]
 
| rowspan="10" | [[14 nm]]
−
| {{intel|Broadwell|l=arch}}
+
! {{intel|Broadwell|l=arch}}
 
| [[Broadwell]]
 
| [[Broadwell]]
 
| 5
 
| 5
−
| 2014-09-05
+
| 2014-09
−
| Broadwell-H<br>Broadwell-U<br>Broadwell-Y
+
| {{intel|Broadwell H|l=core}}<br>{{intel|Broadwell U|l=core}}<br>{{intel|Broadwell Y|l=core}}
−
| Broadwell-DT
+
| {{intel|Broadwell DT|l=core}}<br>''{{intel|Broadwell DE|l=core}}''
−
| [[Core i7-6950X|Broadwell-E]]
+
| {{intel|Broadwell E|l=core}}
−
| Broadwell-EP
+
| {{intel|Broadwell EP|l=core}}<br>('''{{intel|Xeon E5}}''' v4)
−
| Broadwell-EX
+
| {{intel|Broadwell EX|l=core}}<br>('''{{intel|Xeon E7}}''' v4)
 
|-
 
|-
−
| {{intel|Skylake|l=arch}}
+
! {{intel|Skylake|l=arch}}
 
| [[Skylake]]
 
| [[Skylake]]
 
| 6
 
| 6
−
| 1
+
| Xeon 1
−
| 2015-08-05
+
| 2015-08
 
| {{intel|Skylake H|l=core}}<br>{{intel|Skylake U|l=core}}<br>{{intel|Skylake Y|l=core}}
 
| {{intel|Skylake H|l=core}}<br>{{intel|Skylake U|l=core}}<br>{{intel|Skylake Y|l=core}}
−
| {{intel|Skylake S|l=core}}
+
| ''{{intel|Skylake DT|l=core}}''<br>{{intel|Skylake S|l=core}}
 
| {{intel|Skylake W|l=core}}<br>{{intel|Skylake X|l=core}}
 
| {{intel|Skylake W|l=core}}<br>{{intel|Skylake X|l=core}}
−
| colspan="2" | {{intel|Skylake SP|l=core}}<br><small>(formerly Skylake-EP/EX)</small> <br>(Xeon Gold, Platinum)
+
| colspan="2" | {{intel|Skylake SP|l=core}}<br><small>(formerly Skylake-EP/EX)</small> <br>('''Xeon''' Gold, Platinum)
 
|-
 
|-
−
| {{intel|Kaby Lake|l=arch}}
+
! {{intel|Kaby Lake|l=arch}}
 
| [[Kaby Lake]]
 
| [[Kaby Lake]]
 
| 7 / 8
 
| 7 / 8
Line 195: Line 195:
 
| colspan="2" | &mdash;
 
| colspan="2" | &mdash;
 
|-
 
|-
−
| {{intel|Coffee Lake|l=arch}}
+
! {{intel|Coffee Lake|l=arch}}
 
| [[Coffee Lake]]
 
| [[Coffee Lake]]
 
| 8 / 9
 
| 8 / 9
Line 202: Line 202:
 
| {{intel|Coffee Lake S|l=core}}
 
| {{intel|Coffee Lake S|l=core}}
 
| {{intel|Coffee Lake W|l=core}}
 
| {{intel|Coffee Lake W|l=core}}
−
| [[Coffee Lake]]<br>(Xeon E)
+
| [[Coffee Lake]]<br>('''{{intel|Xeon}}''' E)
 
| &mdash;
 
| &mdash;
 
|-
 
|-
−
| {{intel|Whiskey Lake|l=arch}}
+
! {{intel|Whiskey Lake|l=arch}}
 
| [[Whiskey Lake]]
 
| [[Whiskey Lake]]
 
| 8
 
| 8
−
| rowspan="2" | 2018-08-28
+
| rowspan="2" | 2018-08
 
| {{intel|Whiskey Lake U|l=core}}
 
| {{intel|Whiskey Lake U|l=core}}
 
| colspan="2" rowspan="2" | &mdash;
 
| colspan="2" rowspan="2" | &mdash;
 
| colspan="2" rowspan="2" | &mdash;
 
| colspan="2" rowspan="2" | &mdash;
 
|-
 
|-
−
| {{intel|Amber Lake|l=arch}}
+
! {{intel|Amber Lake|l=arch}}
 
| [[Amber Lake]]
 
| [[Amber Lake]]
 
| 8 / 10
 
| 8 / 10
 
| {{intel|Amber Lake Y|l=core}}
 
| {{intel|Amber Lake Y|l=core}}
 
|-
 
|-
−
| {{intel|Cascade Lake|l=arch}}
+
! {{intel|Cascade Lake|l=arch}}
 
| [[Cascade Lake]]
 
| [[Cascade Lake]]
 
| &mdash;
 
| &mdash;
−
| 2
+
| Xeon 2
−
| 2019-04-02
+
| 2019-04
 
| colspan="2" | &mdash;
 
| colspan="2" | &mdash;
 
| {{intel|Cascade Lake W|l=core}}<br>{{intel|Cascade Lake X|l=core}}
 
| {{intel|Cascade Lake W|l=core}}<br>{{intel|Cascade Lake X|l=core}}
−
| colspan="2" | {{intel|Cascade Lake AP|l=core}}<br>{{intel|Cascade Lake SP|l=core}}
+
| colspan="2" | {{intel|Cascade Lake AP|l=core}}<br>{{intel|Cascade Lake SP|l=core}} ('''Xeon''')
 
|-
 
|-
−
| {{intel|Comet Lake|l=arch}}
+
! {{intel|Comet Lake|l=arch}}
 
| [[Comet Lake]]
 
| [[Comet Lake]]
 
| 10
 
| 10
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| colspan="2" | &mdash;
 
| colspan="2" | &mdash;
 
|-
 
|-
−
| {{intel|Cooper Lake|l=arch}}
+
! {{intel|Cooper Lake|l=arch}}
 
| [[Cooper Lake]]
 
| [[Cooper Lake]]
 
| &mdash;
 
| &mdash;
−
| 3
+
| Xeon 3
 
| 2020-06
 
| 2020-06
 
| colspan="4" | &mdash;
 
| colspan="4" | &mdash;
 
| {{intel|Cooper Lake SP|l=core}}
 
| {{intel|Cooper Lake SP|l=core}}
 
|-
 
|-
−
| {{intel|Rocket Lake|l=arch}}
+
! {{intel|Rocket Lake|l=arch}}
 
| {{intel|Cypress Cove|l=core}}
 
| {{intel|Cypress Cove|l=core}}
 
| 11
 
| 11
Line 253: Line 253:
 
| {{intel|Rocket Lake SP|l=core}}
 
| {{intel|Rocket Lake SP|l=core}}
 
| {{intel|Rocket Lake W|l=core}}
 
| {{intel|Rocket Lake W|l=core}}
−
| {{intel|Rocket Lake|l=arch}}<br>(Xeon E)
+
| {{intel|Rocket Lake|l=arch}}<br>('''{{intel|Xeon}}''' E)
 
| &mdash;
 
| &mdash;
 
|-
 
|-
 
| rowspan=4 | [[10 nm]]
 
| rowspan=4 | [[10 nm]]
−
| [[Cannon Lake]]
+
! [[Cannon Lake]]
 
| [[Palm Cove]]
 
| [[Palm Cove]]
 
| 8
 
| 8
Line 265: Line 265:
 
| colspan=2 | &mdash;
 
| colspan=2 | &mdash;
 
|-
 
|-
−
| [[Ice Lake]]<br><small>(client)</small><br><small>(server)</small>
+
! [[Ice Lake]]<br><small>(client)</small><br><small>(server)</small>
 
| rowspan=2 | [[Sunny Cove]]<br>.<hr>.<br>+ 4x {{intel|Tremont|l=arch}}
 
| rowspan=2 | [[Sunny Cove]]<br>.<hr>.<br>+ 4x {{intel|Tremont|l=arch}}
 
| 10
 
| 10
−
| 3
+
| Xeon 3
 
| 2019-09<br><small>(client)</small><br>2021-04<br><small>(server)</small>
 
| 2019-09<br><small>(client)</small><br>2021-04<br><small>(server)</small>
 
| {{intel|Ice Lake U|l=core}}<br>{{intel|Ice Lake Y|l=core}}
 
| {{intel|Ice Lake U|l=core}}<br>{{intel|Ice Lake Y|l=core}}
Line 276: Line 276:
 
| &mdash;
 
| &mdash;
 
|-
 
|-
−
| {{intel|Lakefield|l=arch}}<br><small>(hybrid)</small><br>({{intel|Foveros}})
+
! {{intel|Lakefield|l=arch}}<br><small>(hybrid)</small><br>({{intel|Foveros}})
 
| &mdash;
 
| &mdash;
 
| rowspan="3" | &mdash;
 
| rowspan="3" | &mdash;
−
| 2020-06-10
+
| 2020-06
 
| {{intel|Lakefield|l=arch}}
 
| {{intel|Lakefield|l=arch}}
 
|
 
|
Line 286: Line 286:
 
| &mdash;
 
| &mdash;
 
|-
 
|-
−
| {{intel|Tiger Lake|l=arch}}
+
! {{intel|Tiger Lake|l=arch}}
 
| {{intel|Willow Cove|l=arch}}
 
| {{intel|Willow Cove|l=arch}}
 
| 11
 
| 11
Line 297: Line 297:
 
|-
 
|-
 
| rowspan="4" | [[Intel]] [[7 nm]]
 
| rowspan="4" | [[Intel]] [[7 nm]]
−
| {{intel|Alder Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Alder Lake|l=arch}}<br><small>(hybrid)</small>
 
| rowspan="2" | {{intel|Golden Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 
| rowspan="2" | {{intel|Golden Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 
| 12
 
| 12
−
| 2021-11-04 <!-- ? "Sunny Cove" -->
+
| 2021-11 <!-- ? "Sunny Cove" -->
 
| Alder Lake-H<br>Alder Lake-HX<br>Alder Lake-U<br>{{intel|Alder Lake M|l=core}}
 
| Alder Lake-H<br>Alder Lake-HX<br>Alder Lake-U<br>{{intel|Alder Lake M|l=core}}
 
| {{intel|Alder Lake S|l=core}}
 
| {{intel|Alder Lake S|l=core}}
Line 306: Line 306:
 
| colspan=2 | &mdash;
 
| colspan=2 | &mdash;
 
|-
 
|-
−
| [[Sapphire Rapids]]
+
! [[Sapphire Rapids]]
 
| &mdash;
 
| &mdash;
−
| 4
+
| Xeon 4
−
| 2023-01-10
+
| 2023-01
 
| colspan=2 | &mdash;
 
| colspan=2 | &mdash;
 
| Sapphire <br>Rapids-WS
 
| Sapphire <br>Rapids-WS
−
| Sapphire <br>Rapids-SP/HBM<br>(Xeon Max)
+
| Sapphire <br>Rapids-SP/HBM<br>('''{{intel|Xeon}}''' Max)
 
| Sapphire <br>Rapids-SP
 
| Sapphire <br>Rapids-SP
 
|-
 
|-
−
| {{intel|Raptor Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Raptor Lake|l=arch}}<br><small>(hybrid)</small>
 
| rowspan="2" | {{intel|Raptor Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 
| rowspan="2" | {{intel|Raptor Cove|l=arch}} (P)<br>{{intel|Gracemont|l=arch}} (E)
 
| 13 / 14 /<br>Series<br> 1 / 2
 
| 13 / 14 /<br>Series<br> 1 / 2
 
| &mdash;
 
| &mdash;
−
| 2022-10-20
+
| 2022-10
 
| Raptor Lake-HX<br>Raptor Lake-PX<br>Raptor Lake U
 
| Raptor Lake-HX<br>Raptor Lake-PX<br>Raptor Lake U
 
| Raptor Lake S
 
| Raptor Lake S
 
| Raptor Lake H<br>Raptor Lake P
 
| Raptor Lake H<br>Raptor Lake P
−
| Raptor Lake<br>(Xeon E)
+
| Raptor Lake<br>('''{{intel|Xeon}}''' E)
 
| rowspan=2 | &mdash;
 
| rowspan=2 | &mdash;
 
|-
 
|-
−
| {{intel|Emerald Rapids|l=arch}}
+
! {{intel|Emerald Rapids|l=arch}}
 
| &mdash;
 
| &mdash;
−
| 5
+
| Xeon 5
−
| 2023-12-14
+
| 2023-12
 
| colspan="3" | &mdash;
 
| colspan="3" | &mdash;
 
| Emerald <br>Rapids-SP
 
| Emerald <br>Rapids-SP
 
|-
 
|-
 
| [[Intel]] [[4 nm]]
 
| [[Intel]] [[4 nm]]
−
| {{intel|Meteor Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Meteor Lake|l=arch}}<br><small>(hybrid)</small>
 
| rowspan="2" | {{intel|Redwood Cove|l=arch}} (P)<br>{{intel|Crestmont|l=arch}} (E)
 
| rowspan="2" | {{intel|Redwood Cove|l=arch}} (P)<br>{{intel|Crestmont|l=arch}} (E)
 
| Ultra <br>Series 1
 
| Ultra <br>Series 1
 
| &mdash;
 
| &mdash;
−
| 2023-12-14
+
| 2023-12
 
| Meteor Lake-H<br>Meteor Lake-U
 
| Meteor Lake-H<br>Meteor Lake-U
 
| colspan="2" | &mdash;
 
| colspan="2" | &mdash;
Line 344: Line 344:
 
|-
 
|-
 
| [[Intel]] [[3 nm]]
 
| [[Intel]] [[3 nm]]
−
| {{intel|Granite Rapids|l=arch}}
+
! {{intel|Granite Rapids|l=arch}}
 
| &mdash;
 
| &mdash;
−
| Xeon 6
+
| '''{{intel|Sierra Forest|Xeon 6|l=arch}}'''
−
| 2024-09-24
+
| 2024-09
 
| colspan="3" | &mdash;
 
| colspan="3" | &mdash;
 
| Granite Rapids-AP<br>Granite Rapids-SP
 
| Granite Rapids-AP<br>Granite Rapids-SP
Line 353: Line 353:
 
|-
 
|-
 
| rowspan="2" | TSMC N3B
 
| rowspan="2" | TSMC N3B
−
| {{intel|Lunar Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Lunar Lake|l=arch}}<br><small>(hybrid)</small>
 
| rowspan="2" | {{intel|Lion Cove|l=arch}} (P)<br>{{intel|Skymont|l=arch}} (E)
 
| rowspan="2" | {{intel|Lion Cove|l=arch}} (P)<br>{{intel|Skymont|l=arch}} (E)
 
| Ultra<br>200V <!-- Core Ultra 200V -->
 
| Ultra<br>200V <!-- Core Ultra 200V -->
Line 362: Line 362:
 
| colspan=2 | &mdash;
 
| colspan=2 | &mdash;
 
|-
 
|-
−
| {{intel|Arrow Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Arrow Lake|l=arch}}<br><small>(hybrid)</small>
 
| Ultra<br>Series 2
 
| Ultra<br>Series 2
−
| 2024-10-24<br><small>(desktop)</small><br>2025-01-06<br><small>(mobile)</small>
+
| 2024-10<br><small>(desktop)</small><br>2025-01<br><small>(mobile)</small>
 
| Arrow Lake-H<br>Arrow Lake-HX<br>Arrow Lake-U
 
| Arrow Lake-H<br>Arrow Lake-HX<br>Arrow Lake-U
 
| Arrow Lake-S
 
| Arrow Lake-S
Line 372: Line 372:
 
|-
 
|-
 
| rowspan="2" | [[Intel]] 18A
 
| rowspan="2" | [[Intel]] 18A
−
| {{intel|Panther Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Panther Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Cougar Cove|l=arch}} (P)<br>{{intel|Darkmont|l=arch}} (E) <!-- Cougar Cove (P-cores), Darkmont (E-cores) -->
 
| {{intel|Cougar Cove|l=arch}} (P)<br>{{intel|Darkmont|l=arch}} (E) <!-- Cougar Cove (P-cores), Darkmont (E-cores) -->
 
| Ultra <br>300 <!-- Core Ultra 300 -->
 
| Ultra <br>300 <!-- Core Ultra 300 -->
Line 382: Line 382:
 
| &mdash;
 
| &mdash;
 
|-
 
|-
−
| {{intel|Diamond Rapids|l=arch}}
+
! {{intel|Diamond Rapids|l=arch}}
−
| {{intel|Panther Cove X|l=arch}} <!-- Panther Cove X, Mountain Stream -->
+
| {{intel|Panther Cove X|l=arch}}<br>(''Mountain Stream'') <!-- Panther Cove X, Mountain Stream -->
 
| &mdash;
 
| &mdash;
−
|  
+
| ?
 
| 2025
 
| 2025
 
| &mdash;
 
| &mdash;
Line 394: Line 394:
 
|-
 
|-
 
| rowspan="2" | TBA<br>(TSMC <br>2&nbsp;nm or<br>Intel 18A)
 
| rowspan="2" | TBA<br>(TSMC <br>2&nbsp;nm or<br>Intel 18A)
−
| {{intel|Nova Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Nova Lake|l=arch}}<br><small>(hybrid)</small>
 
| {{intel|Coyote Cove|l=arch}} <!-- Coyote Cove (P), Arctic Wolf (E) -->
 
| {{intel|Coyote Cove|l=arch}} <!-- Coyote Cove (P), Arctic Wolf (E) -->
 
|  
 
|  
Line 405: Line 405:
 
| &mdash;
 
| &mdash;
 
|-
 
|-
−
| {{intel|Razer Lake|l=arch}}<br><small>(hybrid)</small>
+
! {{intel|Razer Lake|l=arch}}<br><small>(hybrid)</small>
 
|  
 
|  
 
|  
 
|  

Latest revision as of 20:00, 1 March 2025

Edit Values
Core µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionApril, 2006
Phase-outMay, 2009
Process65 nm
Instructions
ISAx86-64
Succession

Core was the microarchitecture for Intel's 65 nm process for desktops and servers as a successor to NetBurst. Core was replaced by the Penryn microarchitecture in late 2008.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Key changes from NetBurst[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Overview[edit]

  • When Core was introduced in 2006, Intel described it as a merger of both P6 and NetBurst.
When scrutinizing the details, it's fairly clear that little was actually borrowed from NetBurst.
In fact, it wasn't until Intel's entirely new microarchitecture Sandy Bridge that a true merger presented itself.
New text document.svg This section requires expansion; you can help adding the missing info.


Intel Core Lines[edit]

See also: Intel and intel/atom
Intel Core (+ Pentium 4) Roadmap
Fab
process 		Micro-
architecture 		Code
names 		Core
Gen 		Scalable
(Xeon)
Gen 		Release
date 		Processors
Mobile Desktop Enthusiast/
Workstation 		1P/2P
Server 		4P/8P
Server
180 nm NetBurst Willamette — 2000-11 — Willamette — Foster Foster MP
130 nm
90 nm 		Northwood
Prescott 		2002-01 Northwood
Mobile 		Northwood
Prescott 		Northwood-XE
Prescott 2M-XE 		Prestonia
Gallatin 		Gallatin
130 nm
90 nm
90 nm
65 nm 		Pentium M
.
.
Pentium D 		Banias
Dothan
Smithfield
Presler 		2004-02 Banias
Dothan 		Smithfield
Presler 		Smithfield-XE
Presler-XE 		Nocona
Irwindale
Paxville 		Potomac
Cranford
Paxville
65 nm Modified
Pentium M 		Yonah
Cedar Mill 		1
(Yonah) 		— 2006-01 Yonah Cedar Mill - Dempsey
Sossaman 		Tulsa
(Xeon)
Intel Core Merom 2 2006-07 Merom
Merom-L 		Conroe Kentsfield Woodcrest
Clovertown 		Tigerton
45 nm Penryn 2007-11 Penryn Wolfdale Yorkfield Harpertown Dunnington
Nehalem Nehalem 1
(Core i) 		2008-11 Clarksfield Lynnfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01 Arrandale Clarkdale Gulftown Westmere EP Westmere EX
Sandy Bridge Sandy Bridge 2 2011-01 Sandy Bridge M Sandy Bridge Sandy Bridge E Sandy Bridge EP —
22 nm Ivy Bridge 3 2012-04 Ivy Bridge M Ivy Bridge Ivy Bridge E Ivy Bridge EP Ivy Bridge EX
Haswell Haswell 4 2013-06 Haswell H
Haswell MB
Haswell ULP
Haswell ULX 		Haswell DT Haswell E Haswell EP Haswell EX
Devil's Canyon 2014-06 — Haswell DT —
14 nm Broadwell Broadwell 5 2014-09 Broadwell H
Broadwell U
Broadwell Y 		Broadwell DT
Broadwell DE 		Broadwell E Broadwell EP
(Xeon E5 v4) 		Broadwell EX
(Xeon E7 v4)
Skylake Skylake 6 Xeon 1 2015-08 Skylake H
Skylake U
Skylake Y 		Skylake DT
Skylake S 		Skylake W
Skylake X 		Skylake SP
(formerly Skylake-EP/EX)
(Xeon Gold, Platinum)
Kaby Lake Kaby Lake 7 / 8 — 2016-10 Kaby Lake G
Kaby Lake H
Kaby Lake U
Kaby Lake Y 		Kaby Lake S Kaby Lake X —
Coffee Lake Coffee Lake 8 / 9 2017-10 Coffee Lake B
Coffee Lake H
Coffee Lake U 		Coffee Lake S Coffee Lake W Coffee Lake
(Xeon E) 		—
Whiskey Lake Whiskey Lake 8 2018-08 Whiskey Lake U — —
Amber Lake Amber Lake 8 / 10 Amber Lake Y
Cascade Lake Cascade Lake — Xeon 2 2019-04 — Cascade Lake W
Cascade Lake X 		Cascade Lake AP
Cascade Lake SP (Xeon)
Comet Lake Comet Lake 10 — 2019-09 Comet Lake H
Comet Lake Y
Comet Lake U 		Comet Lake S Comet Lake W —
Cooper Lake Cooper Lake — Xeon 3 2020-06 — Cooper Lake SP
Rocket Lake Cypress Cove 11 — 2021-03 — Rocket Lake SP Rocket Lake W Rocket Lake
(Xeon E) 		—
10 nm Cannon Lake Palm Cove 8 2018-05 Cannon Lake U — —
Ice Lake
(client)
(server) 		Sunny Cove
.
.
+ 4x Tremont 		10 Xeon 3 2019-09
(client)
2021-04
(server) 		Ice Lake U
Ice Lake Y 		— Ice Lake W Ice Lake SP —
Lakefield
(hybrid)
(Foveros) 		— — 2020-06 Lakefield —
Tiger Lake Willow Cove 11 2020-09 Tiger Lake-H
Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4 		—
Intel 7 nm Alder Lake
(hybrid) 		Golden Cove (P)
Gracemont (E) 		12 2021-11 Alder Lake-H
Alder Lake-HX
Alder Lake-U
Alder Lake M 		Alder Lake S Alder Lake P —
Sapphire Rapids — Xeon 4 2023-01 — Sapphire
Rapids-WS 		Sapphire
Rapids-SP/HBM
(Xeon Max) 		Sapphire
Rapids-SP
Raptor Lake
(hybrid) 		Raptor Cove (P)
Gracemont (E) 		13 / 14 /
Series
1 / 2 		— 2022-10 Raptor Lake-HX
Raptor Lake-PX
Raptor Lake U 		Raptor Lake S Raptor Lake H
Raptor Lake P 		Raptor Lake
(Xeon E) 		—
Emerald Rapids — Xeon 5 2023-12 — Emerald
Rapids-SP
Intel 4 nm Meteor Lake
(hybrid) 		Redwood Cove (P)
Crestmont (E) 		Ultra
Series 1 		— 2023-12 Meteor Lake-H
Meteor Lake-U 		— —
Intel 3 nm Granite Rapids — Xeon 6 2024-09 — Granite Rapids-AP
Granite Rapids-SP 		—
TSMC N3B Lunar Lake
(hybrid) 		Lion Cove (P)
Skymont (E) 		Ultra
200V 		— 2024-09 Lunar Lake-V — —
Arrow Lake
(hybrid) 		Ultra
Series 2 		2024-10
(desktop)
2025-01
(mobile) 		Arrow Lake-H
Arrow Lake-HX
Arrow Lake-U 		Arrow Lake-S — —
Intel 18A Panther Lake
(hybrid) 		Cougar Cove (P)
Darkmont (E) 		Ultra
300 		2025 Panther Lake-H
Panther Lake-HL
Panther Lake-U
Panther Lake-UL 		 ? — —
Diamond Rapids Panther Cove X
(Mountain Stream) 		—  ? 2025 — — —
TBA
(TSMC
2 nm or
Intel 18A) 		Nova Lake
(hybrid) 		Coyote Cove — 2026 — TBA TBA — —
Razer Lake
(hybrid) 		— 2027 — TBA TBA — —

Die Shot[edit]

Dual-core Core[edit]

  • Woodcrest
  • 143 mm²
  • 291,000,000 transistors
  • 65 nm process
  • 2 cores
intel woodcrest die shot.jpg

Documents[edit]


Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/core_(client)&oldid=102882"
Facts about "Core - Microarchitectures - Intel"
RDF feed
codenameCore +
designerIntel +
first launchedApril 2006 +
full page nameintel/microarchitectures/core (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCore +
phase-outMay 2009 +
process65 nm (0.065 μm, 6.5e-5 mm) +