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=== KaiXian ZX-A ===
 
=== KaiXian ZX-A ===
 
{{main|via_technologies/microarchitectures/isaiah|l1=VIA's Isaiah}}
 
{{main|via_technologies/microarchitectures/isaiah|l1=VIA's Isaiah}}
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KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as [[VIA Technologies]] {{via|Isaiah|l=arch}} and where manufactured on a [[40 nm process]]. For all practical purposes, those chips are identical to VIA's {{via|Nano}} parts.
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KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as [[VIA Technologies]] {{via|Isaiah|l=arch}} and were manufactured on a [[40 nm process]]. For all practical purposes, those chips are identical to VIA's {{via|Nano}} parts.
  
 
=== KaiXian ZX-B ===
 
=== KaiXian ZX-B ===
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=== KaiXian KX-5000 ===
 
=== KaiXian KX-5000 ===
 
{{main|zhaoxin/microarchitectures/wudaokou|l1=WuDaoKou microarchitecture}}
 
{{main|zhaoxin/microarchitectures/wudaokou|l1=WuDaoKou microarchitecture}}
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Announced at the end of 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are baased on {{zhaoxin|WuDaoKou|l=arch}}, fabricated on [[HLMC]]'s 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the [[GPU]] and [[memory controller]] on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding.
+
Announced at Semicon China 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are based on {{zhaoxin|WuDaoKou|l=arch}}, fabricated on [[HLMC]]'s 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the [[GPU]] and [[memory controller]] on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding.
  
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* '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SHA, AVX, and AVX2)
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* '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
 
* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}}
 
* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}}
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* '''Mem:''' Up 64 GiB of dual-channel 2311 MT/s DDR4
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* '''Mem:''' Up 64 GiB of dual-channel 2133 MT/s DDR4
  
 
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{{comp table count|ask=[[Category:microprocessor models by zhaoxin]] [[microarchitecture::WuDaoKou]] [[series::KX-5000]]}}
 
{{comp table count|ask=[[Category:microprocessor models by zhaoxin]] [[microarchitecture::WuDaoKou]] [[series::KX-5000]]}}
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</table>
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{{comp table end}}
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=== KaiXian KX-6000 ===
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{{main|zhaoxin/microarchitectures/lujiazui|l1=LuJiaZui microarchitecture}}
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The KX-6000 (formerly ZX-E) is a planned series of processors based on {{zhaoxin|LuJiaZui|l=arch}} set to be fabricated on [[TSMC]]'s [[16 nm]].
 +
 +
* '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
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* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}}
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* '''Mem:''' Up 64 GiB of dual-channel 3200 MT/s DDR4
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
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<table class="comptable sortable tc3">
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{{comp table header|main|4:List of LuJiaZui-based KaiXian Processors}}
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{{comp table header|cols|Launched|Cores|L2|%Frequency}}
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{{#ask: [[Category:microprocessor models by zhaoxin]] [[microarchitecture::LuJiaZui]] [[series::KX-6000]]
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|?full page name
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|?model number
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|?first launched
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|?core count
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|?l2$ size
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|?base frequency#GHz
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|?max memory#GiB
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|?has ecc memory support
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|format=template
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|template=proc table 3
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|userparam=6
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|mainlabel=-
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}}
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{{comp table count|ask=[[Category:microprocessor models by zhaoxin]] [[microarchitecture::LuJiaZui]] [[series::KX-6000]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

Latest revision as of 07:23, 27 May 2019

KaiXian
Developer Zhaoxin, VIA Technologies
Manufacturer TSMC, HLMC
Type Microprocessors
Introduction 2016 (announced)
2016 (launch)
ISA x86
µarch Isaiah, Zhangjiang, WuDaoKou, LuJiaZui
Word size 64 bit
8 octets
16 nibbles
Process 40 nm
0.04 μm
4.0e-5 mm
, 28 nm
0.028 μm
2.8e-5 mm
Technology CMOS
Succession
←
QuadCore

KaiXian (ZX/KX) is a family of x86 microprocessors developed by Zhaoxin for the Chinese market.

Overview[edit]

KaiXian is a family of x86 microprocessors designed by Zhaoxin as part of China's national security initiative which attempts to reduce the reliance on foreign technology (e.g., Intel) and to gain greater control over their intellectual property. Those processors are x86-compatible with Intel's processors and are capable of booting all modern operating systems such as Red Hat Enterprise Linux and Windows 10.

Models[edit]

KaiXian ZX-A[edit]

Main article: VIA's Isaiah

KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as VIA Technologies Isaiah and were manufactured on a 40 nm process. For all practical purposes, those chips are identical to VIA's Nano parts.

KaiXian ZX-B[edit]

ZX-B series models were identical to ZX-A except that they are fabricated in mainland China on HLMC's 40 nm process.

KaiXian ZX-C[edit]

Main article: ZhangJiang microarchitecture

ZX-C which is based on the ZhangJiang microarchitecture introduced a number of enhancements including extending the architecture to support up to 8 cores. With many respect they are very similar to VIA's QuadCore. Since those parts were manufactured on TSMC's 28 nm process, they have lower power consumption and thus higher clock speed.

KaiXian KX-5000[edit]

Main article: WuDaoKou microarchitecture

Announced at Semicon China 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are based on WuDaoKou, fabricated on HLMC's 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the GPU and memory controller on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding.

  • ISA: Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
  • Tech: VT-x/EPT, TXT
  • Mem: Up 64 GiB of dual-channel 2133 MT/s DDR4
 List of WuDaoKou-based KaiXian Processors
ModelLaunchedCoresL2Frequency
KX-554028 December 201744 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
KX-564028 December 201744 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
2 GHz
2,000 MHz
2,000,000 kHz
KX-U558028 December 201788 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
KX-U5580M28 December 201788 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
KX-U568028 December 201788 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
2 GHz
2,000 MHz
2,000,000 kHz
Count: 5

KaiXian KX-6000[edit]

Main article: LuJiaZui microarchitecture

The KX-6000 (formerly ZX-E) is a planned series of processors based on LuJiaZui set to be fabricated on TSMC's 16 nm.

  • ISA: Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
  • Tech: VT-x/EPT, TXT
  • Mem: Up 64 GiB of dual-channel 3200 MT/s DDR4
 List of LuJiaZui-based KaiXian Processors
ModelLaunchedCoresL2Frequency
KX-U688088 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
3 GHz
3,000 MHz
3,000,000 kHz
Count: 1

See Also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/kaixian&oldid=91239"
Facts about "KaiXian (ZX/KX) - Zhaoxin"
RDF feed
designerZhaoxin + and VIA Technologies +
first announced2016 +
first launched2016 +
full page namezhaoxin/kaixian +
instance ofmicroprocessor family +
instruction set architecturex86 +
main designerZhaoxin +
manufacturerTSMC + and HLMC +
microarchitectureIsaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui +
nameKaiXian +
process40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +