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KaiXian KX-5540 - Zhaoxin
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KaiXian KX-5540
KX-5540.png
KX-5540 front
General Info
DesignerZhaoxin
ManufacturerHLMC
Model NumberKX-5540
Part NumberKX-5540
MarketDesktop, Mobile, Embedded
IntroductionDecember 28, 2017 (announced)
December 28, 2017 (launched)
General Specs
FamilyKaiXian
SeriesKX-5000
Frequency1,800 MHz
Bus typePCIe 3.0
Bus rate4 × 8 GT/s
Clock multiplier18
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWuDaoKou
Process28 nm
Transistors2,100,000,000
TechnologyCMOS
Die187 mm²
Word Size64 bit
Cores4
Threads4
Max CPUs1 (Uniprocessor)
Max Memory64 GiB
Electrical
Tjunction0 °C – 90 °C

KaiXian KX-5540 is a 64-bit quad-core x86 microprocessor designed by Zhaoxin and introduced in late 2017 specifically for the Chinese market. This processor is fabricated on a 28 nm process based on the WuDaoKou microarchitecture. The KX-5640 operates at 1.8 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-2133 memory. The KX-5540 also incorporates an integrated graphics processor.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: WuDaoKou § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB8-way set associative 
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB8-way set associative 

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB32-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 3.0
Max Lanes: 24


Graphics[edit]

[Edit/Modify IGP Info]

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Integrated Graphics Information
GPU?
DesignerZhaoxin
Max Displays3
Frequency? MHz
"? MHz" is not a number.
OutputDisplayPort, Embedded DisplayPort, HDMI, VGA

Max Resolution
HDMI4096x2304
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz

Standards
DirectX11.1
DP1.2a
eDP1.3
HDMI1.4b

Features[edit]

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
KaiXian KX-5540 - Zhaoxin#pcie +
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typePCIe 3.0 +
clock multiplier18 +
core count4 +
designerZhaoxin +
die area187 mm² (0.29 in², 1.87 cm², 187,000,000 µm²) +
familyKaiXian +
first announcedDecember 28, 2017 +
first launchedDecember 28, 2017 +
full page namezhaoxin/kaixian/kx-5540 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Trusted Execution Technology +, Intel VT-x + and Extended Page Tables +
has intel trusted execution technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpu? +
integrated gpu designerZhaoxin +
isax86-64 +
isa familyx86 +
l1$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1d$ description8-way set associative +
l1d$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ description32-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateDecember 28, 2017 +
main imageFile:KX-5540.png +
main image captionKX-5540 front +
manufacturerHLMC +
market segmentDesktop +, Mobile + and Embedded +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory channels2 +
microarchitectureWuDaoKou +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberKX-5540 +
nameKaiXian KX-5540 +
part numberKX-5540 +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesKX-5000 +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count4 +
transistor count2,100,000,000 +
word size64 bit (8 octets, 16 nibbles) +