|Developer||Zhaoxin, VIA Technologies|
|Introduction|| 2016 (announced)|
|µarch||Isaiah, Zhangjiang, WuDaoKou, LuJiaZui|
|Word size|| 64 bit|
|Process|| 40 nm|
0.04 μm, 28 nm
KaiXian is a family of x86 microprocessors designed by Zhaoxin as part of China's national security initiative which attempts to reduce the reliance on foreign technology (e.g., Intel) and to gain greater control over their intellectual property. Those processors are x86-compatible with Intel's processors and are capable of booting all modern operating systems such as Red Hat Enterprise Linux and Windows 10.
- Main article: VIA's Isaiah
KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as VIA Technologies Isaiah and where manufactured on a 40 nm process. For all practical purposes, those chips are identical to VIA's Nano parts.
- Main article: ZhangJiang microarchitecture
ZX-C which is based on the ZhangJiang microarchitecture introduced a number of enhancements including extending the architecture to support up to 8 cores. With many respect they are very similar to VIA's QuadCore. Since those parts were manufactured on TSMC's 28 nm process, they have lower power consumption and thus higher clock speed.
- Main article: WuDaoKou microarchitecture
Announced at Semicon China 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are based on WuDaoKou, fabricated on HLMC's 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the GPU and memory controller on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding.
- ISA: Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
- Tech: VT-x/EPT, TXT
- Mem: Up 64 GiB of dual-channel 2133 MT/s DDR4
|List of WuDaoKou-based KaiXian Processors|
|KX-5540||28 December 2017||4||4 MiB|
|KX-5640||28 December 2017||4||4 MiB|
|KX-U5580||28 December 2017||8||8 MiB|
|KX-U5580M||28 December 2017||8||8 MiB|
|KX-U5680||28 December 2017||8||8 MiB|
- Main article: LuJiaZui microarchitecture
|designer||Zhaoxin + and VIA Technologies +|
|first announced||2016 +|
|first launched||2016 +|
|full page name||zhaoxin/kaixian +|
|instance of||microprocessor family +|
|instruction set architecture||x86 +|
|manufacturer||TSMC + and HLMC +|
|microarchitecture||Isaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui +|
|process||40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +|
|word size||64 bit (8 octets, 16 nibbles) +|