Edit Values
KaiXian KX-U6880
KX-U6880 front
General Info
Designer	Zhaoxin
Manufacturer	TSMC
Model Number	KX-U6880
Part Number	KX-U6880
Market	Desktop, Mobile, Embedded
Introduction	September, 2018 (announced)
General Specs
Family	KaiXian
Series	KX-6000
Frequency	3,000 MHz
Bus type	PCIe 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	30
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	LuJiaZui
Process	16 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Max Memory	64 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)

KaiXian KX-U6880 is a 64-bit octa-core x86 microprocessor designed by Zhaoxin and announced in late 2018 specifically for the Chinese market. This processor is fabricated on a 16 nm process based on the LuJiaZui microarchitecture. The KX-U6880 operates at 3 GHz with a TDP of ? W and supports up to 64 GiB of dual-channel DDR4-3200 memory. The KX-U6880 also incorporates an integrated graphics processor.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: LuJiaZui § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L2$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     2x4 MiB 32-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3200 Supports ECC No Max Mem 64 GiB Controllers 1 Channels 2 Max Bandwidth 47.68 GiB/s 48,824.32 MiB/s 51.196 GB/s 51,196.01 MB/s 0.0466 TiB/s 0.0512 TB/s Bandwidth Single 23.84 GiB/s Double 47.68 GiB/s

Expansions

This chip has 16 PCIe 3.0 lanes, two SATA 3.0 interfaces, two USB 3.1 Gen 1, and four USB 2.0 ports.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 16

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU ? Designer Zhaoxin Max Displays 3 Frequency ? MHz "? MHz" is not a number. Output DP, eDP, HDMI, VGA Max Resolution HDMI 4096x2304 DP 4096x2304 @60 Hz eDP 4096x2304 @60 Hz Standards DirectX 11.1 DP 1.2a eDP 1.3 HDMI 1.4b

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute TXT Trusted Execution Technology (SMX) VT-x VT-x (Virtualization) EPT Extended Page Tables (SLAT)