Semiconductor & Computer Engineering
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Difference between revisions of "64-bit architecture"
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== 64-bit microprocessors == | == 64-bit microprocessors == | ||
| + | {| border="0" cellpadding="5" width="75%" | ||
| + | |- | ||
| + | |width="25%" valign="top" align="left"| | ||
=== [[Alpha]] === | === [[Alpha]] === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
| − | '''DEC''' | + | '''[[DEC]]''' |
* {{decc|Alpha}} | * {{decc|Alpha}} | ||
</div> | </div> | ||
| − | |||
| − | |||
=== [[ARM]] === | === [[ARM]] === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
| − | '''MediaTek''' | + | '''[[MediaTek]]''' |
* {{mediatek|Helio}} | * {{mediatek|Helio}} | ||
| − | '''Phytium''' | + | '''[[Phytium]]''' |
* {{phytium|FT-1500A}} | * {{phytium|FT-1500A}} | ||
</div> | </div> | ||
| − | + | |width="25%" valign="top" align="left"| | |
=== [[MIPS]] === | === [[MIPS]] === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
| − | '''Cavium''' | + | '''[[Cavium]]''' |
{{collist | {{collist | ||
| count = 1 | | count = 1 | ||
| Line 29: | Line 30: | ||
}} | }} | ||
</div> | </div> | ||
| − | |||
=== [[POWER]] === | === [[POWER]] === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
| − | '''IBM''' | + | '''[[IBM]]''' |
{{collist | {{collist | ||
| count=1 | | count=1 | ||
| Line 41: | Line 41: | ||
}} | }} | ||
</div> | </div> | ||
| + | |width="25%" valign="top" align="left"| | ||
| + | === [[SPARC]] === | ||
| + | <div style="margin: 30px;"> | ||
| + | '''[[Fujitsu]]''' | ||
| + | * {{fujitsu|SPARC64}} | ||
| + | '''[[Oracle]]''' | ||
| + | * {{oracle|SPARC}} | ||
| + | '''[[Sun Microsystems]]''' | ||
| + | * {{sun|UltraSPARC}} | ||
| + | </div> | ||
| + | |} | ||
=== [[x86]] === | === [[x86]] === | ||
| − | + | {{collist | |
| − | '''AMD''' | + | | style = padding-left: 20px |
| − | + | | count = 3 | |
| − | {{#ask: [[Category:all | + | | |
| + | '''[[AMD]]''' | ||
| + | {{#ask: [[Category:all microarchitectures]] [[designer::AMD]] [[instruction set architecture::x86-64]] | ||
| + | | ?full page name | ||
| + | | ?name | ||
| + | | sort= first launched | ||
| + | | format=template | ||
| + | | template=list item | ||
| + | | mainlabel=- | ||
| + | | userparam=1 | ||
| + | }} | ||
| + | '''[[Intel]]''' | ||
| + | {{#ask: [[Category:all microarchitectures]] [[designer::Intel]] [[instruction set architecture::x86-64]] | ||
| + | | ?full page name | ||
| + | | ?name | ||
| sort= first launched | | sort= first launched | ||
| format=list | | format=list | ||
| + | | format=template | ||
| + | | template=list item | ||
| + | | mainlabel=- | ||
| + | | userparam=1 | ||
}} | }} | ||
| − | + | }} | |
| − | '''Intel''' | + | {{clear}} |
| − | + | === [[IA-64]] === | |
| − | {{#ask: [[Category:all | + | {{collist |
| + | | style = padding-left: 20px | ||
| + | | count = 3 | ||
| + | | | ||
| + | '''[[Intel]]''' | ||
| + | {{#ask: [[Category:all microarchitectures]] [[designer::Intel]] [[instruction set architecture::IA-64]] | ||
| + | | ?full page name | ||
| + | | ?name | ||
| sort= first launched | | sort= first launched | ||
| format=list | | format=list | ||
| + | | format=template | ||
| + | | template=list item | ||
| + | | mainlabel=- | ||
| + | | userparam=1 | ||
| + | }} | ||
}} | }} | ||
| − | |||
=== Other === | === Other === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
| − | + | '''[[NEC]] SX''' | |
| + | * [[nec/microarchitectures/sx-aurora|SX-Aurora]] | ||
</div> | </div> | ||
| + | |||
=== Research/University === | === Research/University === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
Latest revision as of 11:00, 29 April 2025
The 64-bit architecture is a microprocessor or computer architecture that has a datapath width or a highest operand width of 64 bits or 8 octets. These architectures typically have a matching register file with registers width of 64 bits.
Contents
64-bit microprocessors[edit]
Alpha[edit]ARM[edit] |
MIPS[edit]POWER[edit] |
SPARC[edit] |
x86[edit]
- Core
- Penryn
- Bonnell
- Nehalem
- Westmere
- Sandy Bridge (client)
- Saltwell
- Ivy Bridge
- Silvermont
- Haswell
- Broadwell
- Airmont
- Skylake (client)
- Kaby Lake
- Goldmont
- Skylake (server)
- Coffee Lake
- Goldmont Plus
- Knights Mill
- Palm Cove
- Amber Lake
- Whiskey Lake
- Cannon Lake
- Sunny Cove
- Lakefield
- Tremont
- Cascade Lake
- Snow Ridge
- Ice Lake (client)
- Willow Cove
- Cooper Lake
- Tiger Lake
- Gracemont
- Alder Lake
- Rocket Lake
- Ice Lake (server)
- Golden Cove
- Ocean Cove
- Raptor Lake
- Emerald Rapids
- Meteor Lake
- Sapphire Rapids
- Granite Rapids
- Sierra Forest
- Diamond Rapids
IA-64[edit]
Other[edit]
Research/University[edit]
- Princeton
This list is incomplete; you can help by expanding it.
64-bit microcontrollers[edit]
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