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{{title|Lake}}'''Lake''' may refer to:
+
{{title|Lake}}
  
−
* [[Intel]]
+
=== Overview ===
−
** Microarchitectures
+
'''Lake''' may refer to:
−
*** Edge
+
{| border="0" cellpadding="5" width="90%"
−
**** {{intel|Lakefield|l=arch}}
+
|-
−
*** Client
+
|width="25%" valign="top" align="left"|
−
**** {{intel|Skylake (client)|Skylake|l=arch}}
+
:; <big>[[Intel]]</big>
−
**** {{intel|Kaby Lake|l=arch}}
 
−
**** {{intel|Coffee Lake|l=arch}}
 
−
**** {{intel|Whiskey Lake|l=arch}}
 
−
**** {{intel|Amber Lake|l=arch}}
 
−
**** {{intel|Comet Lake|l=arch}}
 
−
**** {{intel|Cannon Lake|l=arch}}
 
−
**** {{intel|Ice Lake (client)|Ice Lake|l=arch}}
 
−
**** {{intel|Tiger Lake|l=arch}}
 
−
**** {{intel|Alder Lake|l=arch}}
 
−
**** {{intel|Rocket Lake|l=arch}}
 
−
**** {{intel|Raptor Lake|l=arch}}
 
−
**** {{intel|Meteor Lake|l=arch}}
 
−
*** Server
 
−
**** {{intel|Skylake (server)|Skylake|l=arch}}
 
−
**** {{intel|Cascade Lake|l=arch}}
 
−
**** {{intel|Cooper Lake|l=arch}}
 
−
**** {{intel|Ice Lake (server)|Ice Lake|l=arch}}
 
−
*** MCU
 
−
**** {{intel|Lakemont|l=arch}}
 
−
** Cores
 
−
*** Client
 
−
**** {{intel|Apollo Lake|l=core}}
 
−
**** {{intel|Gemini Lake|l=core}}
 
−
**** {{intel|Mercury Lake|l=core}}
 
−
**** {{intel|Elkhart Lake|l=core}}
 
−
**** Skylake
 
−
***** {{intel|Skylake DT|l=core}}
 
−
***** {{intel|Skylake S|l=core}}
 
−
***** {{intel|Skylake H|l=core}}
 
−
***** {{intel|Skylake U|l=core}}
 
−
***** {{intel|Skylake Y|l=core}}
 
−
*** Kaby Lake
 
−
***** {{intel|Kaby Lake X|l=core}}
 
−
***** {{intel|Kaby Lake DT|l=core}}
 
−
***** {{intel|Kaby Lake R|l=core}}
 
−
***** {{intel|Kaby Lake S|l=core}}
 
−
***** {{intel|Kaby Lake G|l=core}}
 
−
***** {{intel|Kaby Lake H|l=core}}
 
−
***** {{intel|Kaby Lake U|l=core}}
 
−
***** {{intel|Kaby Lake Y|l=core}}
 
−
*** Coffee Lake
 
−
***** {{intel|Coffee Lake ER|l=core}}
 
−
***** {{intel|Coffee Lake E|l=core}}
 
−
***** {{intel|Coffee Lake R|l=core}}
 
−
***** {{intel|Coffee Lake S|l=core}}
 
−
***** {{intel|Coffee Lake HR|l=core}}
 
−
***** {{intel|Coffee Lake H|l=core}}
 
−
***** {{intel|Coffee Lake U|l=core}}
 
−
*** Whiskey Lake
 
−
**** {{intel|Whiskey Lake U|l=core}}
 
−
*** Amber Lake
 
−
**** {{intel|Amber Lake Y|l=core}}
 
−
*** Ice Lake
 
−
**** {{intel|Ice Lake U|l=core}}
 
−
**** {{intel|Ice Lake Y|l=core}}
 
−
*** Server
 
−
**** Skylake
 
−
***** {{intel|Skylake SP|l=core}}
 
−
***** {{intel|Skylake X|l=core}}
 
−
***** {{intel|Skylake W|l=core}}
 
−
***** {{intel|Skylake DE|l=core}}
 
−
**** Cascade Lake
 
−
***** {{intel|Cascade Lake AP|l=core}}
 
−
***** {{intel|Cascade Lake SP|l=core}}
 
−
***** {{intel|Cascade Lake R|l=core}}
 
−
***** {{intel|Cascade Lake X|l=core}}
 
−
***** {{intel|Cascade Lake W|l=core}}
 
−
**** Ice Lake
 
−
***** {{intel|Ice Lake SP|l=core}}
 
−
** IGPs
 
−
*** {{intel|Ironlake}}
 
−
** Platforms
 
−
*** {{intel|Rock Lake|l=platform}}
 
−
* Intel Nervana
 
−
** {{nervana|Lake Crest|l=arch}}
 
  
−
=== Intel CPU Core Roadmap ===
+
:; Nervana
 +
* {{nervana|Lake Crest|l=arch}}
 +
:; IGPs
 +
* {{intel|Ironlake}}
 +
 
 +
:; Platforms
 +
* {{intel|Rock Lake|l=platform}}
 +
|width="25%" valign="top" align="left"|
 +
:; '''[[Microarchitectures]]'''
 +
 
 +
:; '''Client'''
 +
* {{intel|Alder Lake|l=arch}}
 +
* {{intel|Amber Lake|l=arch}}
 +
* {{intel|Comet Lake|l=arch}}
 +
* {{intel|Cannon Lake|l=arch}}
 +
* {{intel|Coffee Lake|l=arch}}
 +
|width="25%" valign="top" align="left"|
 +
* {{intel|Skylake (client)|Skylake|l=arch}}
 +
* {{intel|Kaby Lake|l=arch}}
 +
* {{intel|Ice Lake (client)|Ice Lake|l=arch}}
 +
* {{intel|Tiger Lake|l=arch}} 
 +
* {{intel|Rocket Lake|l=arch}}
 +
* {{intel|Raptor Lake|l=arch}}
 +
* {{intel|Meteor Lake|l=arch}}
 +
* {{intel|Whiskey Lake|l=arch}}
 +
|width="25%" valign="top" align="left"|
 +
:; '''Server'''
 +
* {{intel|Skylake (server)|Skylake|l=arch}}
 +
* {{intel|Cascade Lake|l=arch}}
 +
* {{intel|Cooper Lake|l=arch}}
 +
* {{intel|Ice Lake (server)|Ice Lake|l=arch}}
 +
: '''Edge''' • {{intel|Lakefield|l=arch}}
 +
: '''MCU''' • {{intel|Lakemont|l=arch}}
 +
|}
 +
----
 +
{| border="0" cellpadding="5" width="90%"
 +
|-
 +
|width="25%" valign="top" align="left"|
 +
:; <big>'''Cores'''</big>
 +
 
 +
:; Client
 +
* [[Amber Lake]]
 +
:• {{intel|Amber Lake Y|l=core}}
 +
* [[Coffee Lake]]
 +
:• {{intel|Coffee Lake ER|l=core}}
 +
:• {{intel|Coffee Lake E|l=core}}
 +
:• {{intel|Coffee Lake R|l=core}}
 +
:• {{intel|Coffee Lake S|l=core}}
 +
:• {{intel|Coffee Lake HR|l=core}}
 +
:• {{intel|Coffee Lake H|l=core}}
 +
:• {{intel|Coffee Lake U|l=core}}
 +
|width="25%" valign="top" align="left"|
 +
* {{intel|Apollo Lake|l=core}}
 +
* {{intel|Elkhart Lake|l=core}}
 +
* {{intel|Gemini Lake|l=core}}
 +
* [[Kaby Lake]]
 +
:• {{intel|Kaby Lake X|l=core}}
 +
:• {{intel|Kaby Lake DT|l=core}}
 +
:• {{intel|Kaby Lake R|l=core}}
 +
:• {{intel|Kaby Lake S|l=core}}
 +
:• {{intel|Kaby Lake G|l=core}}
 +
:• {{intel|Kaby Lake H|l=core}}
 +
:• {{intel|Kaby Lake U|l=core}}
 +
:• {{intel|Kaby Lake Y|l=core}}
 +
|width="25%" valign="top" align="left"|
 +
* [[Skylake]]
 +
:• {{intel|Skylake DT|l=core}}
 +
:• {{intel|Skylake S|l=core}}
 +
:• {{intel|Skylake H|l=core}}
 +
:• {{intel|Skylake U|l=core}}
 +
:• {{intel|Skylake Y|l=core}}
 +
* [[Whiskey Lake]]
 +
:• {{intel|Whiskey Lake U|l=core}}
 +
* [[Ice Lake]]
 +
:• {{intel|Ice Lake U|l=core}}
 +
:• {{intel|Ice Lake Y|l=core}}
 +
* {{intel|Mercury Lake|l=core}}
 +
|width="25%" valign="top" align="left"|
 +
:; '''Server'''
 +
* [[Skylake]]
 +
:• {{intel|Skylake SP|l=core}}
 +
:• {{intel|Skylake X|l=core}}
 +
:• {{intel|Skylake W|l=core}}
 +
:• {{intel|Skylake DE|l=core}}
 +
* [[Cascade Lake]]
 +
:• {{intel|Cascade Lake AP|l=core}}
 +
:• {{intel|Cascade Lake SP|l=core}}
 +
:• {{intel|Cascade Lake R|l=core}}
 +
:• {{intel|Cascade Lake X|l=core}}
 +
:• {{intel|Cascade Lake W|l=core}}
 +
* [[Ice Lake]] • {{intel|Ice Lake SP|l=core}}
 +
|}
 +
 
 +
== Intel CPU Core Roadmap ==
 
{{see also|Intel Atom|intel/core}}
 
{{see also|Intel Atom|intel/core}}
 
<!--
 
<!--
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     <tr>
 
     <tr>
 
         <th>[[Microarchitecture|Microarch]]</th>
 
         <th>[[Microarchitecture|Microarch]]</th>
−
         <th>Step</th>
+
         <th>Core/Step</th>
 
         <th>[[Microarchitecture|Microarch]]</th>
 
         <th>[[Microarchitecture|Microarch]]</th>
−
         <th>Step</th>
+
         <th>Core/Step</th>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
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</ul> -->
 
</ul> -->
 
}}
 
}}
 +
 
[[File:sunny cove roadmap.png]]
 
[[File:sunny cove roadmap.png]]
 +
 +
===See also===
 +
:;[[Intel]] • {{intel|CPUID}}
 +
*{{intel|Atom}}
 +
*{{intel|Core|l=arch}}
 +
*{{intel|Celeron}}
 +
*{{intel|Pentium}}
 +
*{{intel|Xeon}}
 +
*[[Lake]]
 +
  
 
{{disambig}}
 
{{disambig}}

Latest revision as of 23:00, 1 March 2025


Overview[edit]

Lake may refer to:

Intel
Nervana
IGPs
Platforms
Microarchitectures
Client
Server
Edge • Lakefield
MCU • Lakemont
Cores
Client
• Amber Lake Y
• Coffee Lake ER
• Coffee Lake E
• Coffee Lake R
• Coffee Lake S
• Coffee Lake HR
• Coffee Lake H
• Coffee Lake U
• Kaby Lake X
• Kaby Lake DT
• Kaby Lake R
• Kaby Lake S
• Kaby Lake G
• Kaby Lake H
• Kaby Lake U
• Kaby Lake Y
• Skylake DT
• Skylake S
• Skylake H
• Skylake U
• Skylake Y
• Whiskey Lake U
• Ice Lake U
• Ice Lake Y
Server
• Skylake SP
• Skylake X
• Skylake W
• Skylake DE
• Cascade Lake AP
• Cascade Lake SP
• Cascade Lake R
• Cascade Lake X
• Cascade Lake W

Intel CPU Core Roadmap[edit]

See also: Intel Atom and intel/core
Intel Atom (ULV) Node name Intel Core/Pentium
Microarch Core/Step Microarch Core/Step
600 nm P6 Pentium Pro
(133 MHz)
500 nm Pentium Pro
(150 MHz)
350 nm Pentium Pro
(166–200 MHz)
Klamath
250 nm Deschutes
Katmai NetBurst
180 nm Coppermine Willamette (P4)
130 nm Tualatin Northwood (P4)
Pentium M Banias NetBurst (HT) NetBurst (×2)
90 nm Dothan Prescott (P4) ⇨ Prescott‑2M ⇨ Smithfield
Tejas/Jayhawk → ⇩ → Cedar Mill (Tejas)
65 nm Yonah Nehalem (NetBurst) Cedar Mill (P4) ⇨ Presler
Core Merom 4 cores on mainstream desktop, DDR3 introduced
Bonnell Bonnell 45 nm Penryn
Nehalem Nehalem Hyper-threading reintroduced, integrated Memory controller,
PCH, L3-cache introduced, 256KB L2-cache/core
Saltwell 32 nm Westmere Introduced GPU on same package and AES-NI
Sandy Bridge Sandy Bridge On-die ring bus, no more non-UEFI motherboards
Silvermont Silvermont 22 nm Ivy Bridge
Haswell Haswell Fully integrated voltage regulator
Airmont 14 nm Broadwell
Skylake Skylake DDR4 introduced on mainstream desktop
Goldmont Goldmont Kaby Lake
Coffee Lake 6 cores on mainstream desktop
Amber Lake Mobile-only
Goldmont Plus Goldmont Plus Whiskey Lake Mobile-only
Coffee Lake Refresh 8 cores on mainstream desktop
Comet Lake 10 cores on mainstream desktop
Rocket Lake Cypress Cove Backported Sunny Cove microarchitecture for 14nm
Tremont Tremont
(Lakefield)		 10 nm Cannon Lake Palm Cove Mobile-only
Ice Lake Sunny Cove 512 KB L2-cache/core
Tiger Lake Willow Cove Intel Xe graphics engine
Gracemont Gracemont Intel 7
(10nm ESF)		 Alder Lake Golden Cove Hybrid, DDR5, PCIe 5.0
Raptor Lake Raptor Cove
Crestmont Crestmont Intel 4 Meteor Lake Redwood Cove Mobile-only, NPU, chiplet architecture
Skymont Skymont N3B (TSMC) Lunar Lake Lion Cove Low power mobile only (9-30W)
Arrow Lake Lion Cove
Darkmont Darkmont 18A Panther Lake Cougar Cove

}}

sunny cove roadmap.png

See also[edit]

Intel • CPUID


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