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== 64-bit microprocessors == | == 64-bit microprocessors == | ||
− | + | === [[Alpha]] === | |
− | === [[ | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
− | ''' | + | '''DEC''' |
− | + | * {{decc|Alpha}} | |
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− | }} | ||
</div> | </div> | ||
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=== [[ARM]] === | === [[ARM]] === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
'''MediaTek''' | '''MediaTek''' | ||
* {{mediatek|Helio}} | * {{mediatek|Helio}} | ||
+ | '''Phytium''' | ||
+ | * {{phytium|FT-1500A}} | ||
</div> | </div> | ||
+ | |||
=== [[MIPS]] === | === [[MIPS]] === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
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| width = 750px | | width = 750px | ||
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− | * {{ | + | * {{cavium|OCTEON}} |
+ | * {{cavium|OCTEON Plus}} | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | === [[POWER]] === | ||
+ | <div style="margin: 30px;"> | ||
+ | '''IBM''' | ||
+ | {{collist | ||
+ | | count=1 | ||
+ | | width=750px | ||
+ | | | ||
+ | * {{ibm|POWER8}} | ||
+ | * {{ibm|POWER9}} | ||
}} | }} | ||
</div> | </div> | ||
+ | |||
+ | === [[SPARC]] === | ||
+ | <div style="margin: 30px;"> | ||
+ | '''Fujitsu''' | ||
+ | * {{fujitsu|SPARC64}} | ||
+ | '''Oracle''' | ||
+ | * {{oracle|SPARC}} | ||
+ | '''Sun Microsystems''' | ||
+ | * {{sun|UltraSPARC}} | ||
+ | </div> | ||
+ | |||
+ | === [[x86]] === | ||
+ | {{collist | ||
+ | | style = padding-left: 20px | ||
+ | | count = 3 | ||
+ | | | ||
+ | '''AMD''' | ||
+ | {{#ask: [[Category:all microarchitectures]] [[designer::AMD]] [[instruction set architecture::x86-64]] | ||
+ | | ?full page name | ||
+ | | ?name | ||
+ | | sort= first launched | ||
+ | | format=template | ||
+ | | template=list item | ||
+ | | mainlabel=- | ||
+ | | userparam=1 | ||
+ | }} | ||
+ | '''Intel''' | ||
+ | {{#ask: [[Category:all microarchitectures]] [[designer::Intel]] [[instruction set architecture::x86-64]] | ||
+ | | ?full page name | ||
+ | | ?name | ||
+ | | sort= first launched | ||
+ | | format=list | ||
+ | | format=template | ||
+ | | template=list item | ||
+ | | mainlabel=- | ||
+ | | userparam=1 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | === [[IA-64]] === | ||
+ | {{collist | ||
+ | | style = padding-left: 20px | ||
+ | | count = 3 | ||
+ | | | ||
+ | '''Intel''' | ||
+ | {{#ask: [[Category:all microarchitectures]] [[designer::Intel]] [[instruction set architecture::IA-64]] | ||
+ | | ?full page name | ||
+ | | ?name | ||
+ | | sort= first launched | ||
+ | | format=list | ||
+ | | format=template | ||
+ | | template=list item | ||
+ | | mainlabel=- | ||
+ | | userparam=1 | ||
+ | }} | ||
+ | }} | ||
+ | |||
=== Other === | === Other === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> | ||
− | ''' | + | '''NEC SX''' |
− | * | + | * [[nec/microarchitectures/sx-aurora|SX-Aurora]] |
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</div> | </div> | ||
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=== Research/University === | === Research/University === | ||
<div style="margin: 30px;"> | <div style="margin: 30px;"> |
Latest revision as of 02:48, 17 March 2019
The 64-bit architecture is a microprocessor or computer architecture that has a datapath width or a highest operand width of 64 bits or 8 octets. These architectures typically have a matching register file with registers width of 64 bits.
Contents
64-bit microprocessors[edit]
Alpha[edit]
DEC
ARM[edit]
MIPS[edit]
Cavium
POWER[edit]
SPARC[edit]
x86[edit]
AMD
Intel
- NetBurst
- Core
- Penryn
- Bonnell
- Nehalem
- Westmere
- Sandy Bridge (client)
- Saltwell
- Ivy Bridge
- Silvermont
- Haswell
- Broadwell
- Airmont
- Skylake (client)
- Kaby Lake
- Goldmont
- Skylake (server)
- Coffee Lake
- Goldmont Plus
- Knights Mill
- Palm Cove
- Amber Lake
- Whiskey Lake
- Cannon Lake
- Cascade Lake
- Snow Ridge
- Sunny Cove
- Lakefield
- Tremont
- Ice Lake (client)
- Willow Cove
- Cooper Lake
- Tiger Lake
- Alder Lake
- Gracemont
- Rocket Lake
- Ice Lake (server)
- Golden Cove
- Ocean Cove
- Raptor Lake
- Emerald Rapids
- Sapphire Rapids
- Meteor Lake
- Granite Rapids
- Sierra Forest
- Diamond Rapids
IA-64[edit]
Other[edit]
NEC SX
Research/University[edit]
- Princeton
This list is incomplete; you can help by expanding it.
64-bit microcontrollers[edit]
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