Latest revision as of 07:39, 3 March 2024

Zen+ (Zen Plus) is the successor to Zen, a 12 nm microarchitecture designed by AMD and introduced in 2018 for the mainstream PC, enthusiast, and server markets. Zen+ was succeeded by Zen 2 in 2019.

Zen+ based processors are sold under the brand 2nd-Generation Ryzen and 2nd-Generation Threadripper.

History[edit]

Zen+ Roadmap

Zen+ succeeded Zen in April of 2018. Zen+ features the same core as Zen but takes advantage of the new GlobalFoundries' 12nm process to deliver higher clock speeds and improved power consumption. Zen+ was initially mentioned by AMD's senior fellow and lead architect of Zen, Michael Clark, during Hot Chips 28 in 2016 as part of AMD's continuing commitment in the high-performance computing market.

Codenames[edit]

Process Technology[edit]

See also: 12 nm process

Zen+ is manufactured on Global Foundries' 12 nm process Leading-Performance (12LP), an enhanced version of their 14nm process. The enhanced process provides up to 15% higher density or up to 10% higher performance. 12LP brings around a 10% frequency bump for the Ryzen lineup at the same power envelopes.

Note that AMD did not switch to standard libraries and instead chose to get whatever added performance they could get from the same physical design as 14 nm. This also means some performance was left on the table and the die size is exactly the same as Zen.

Compatibility[edit]

Linux added initial support for Zen starting with Linux Kernel 4.10. Microsoft officially only supports Zen on Windows 10. Windows 7 and 8 drivers are available for many mainboards. But drivers must be integrated into the installation image or installed first before switching to a Zen-based system. Otherwise support for any kind of USB device like keyboard and mouse would be missing.

Compiler support[edit]

Zen+ is largely the same architecture as Zen and thus uses the same compiler switches.

CPUID[edit]

Release Dates[edit]

AMD launched 2nd generation Ryzen on the 19th April of 2018. 2nd Generation Ryzen Threadripper was introduced in August 2018 and Ryzen PRO processors has launched in the second half of 2018.

Architecture[edit]

Serving as a light refresh over Zen, those processors have around ten percent higher base frequency for the same power envelope.

Key changes from Zen[edit]

• ~10% higher clock frequency
• ~3% single-thread IPC improvement
• 12 nm process (from 14 nm)
• Precision Boost 2 (from Precision Boost)
  • Precision Boost Overdrive
• XFR 2 (from XFR 1)
• Cache
  • Improved cache prefetch
  • 12 cycle L2 latency for mainstream desktop (from 17 cycles)
• Memory
  • Higher DDR4 transfer rate (2933 MT/s from 2666 MT/s)
• Mainstream chipsets (See § Sockets/Platform)
  • X370 → X470
    • New StoreMI Technology
    • Lower Power
    • Bug fixes
    • OEM related issues resolved (unspecified)
• Family
  • Threadripper: 2x cores (up to 32, from 16)

Block Diagram[edit]

Entire SoC Overview[edit]

Individual Core[edit]

Memory Hierarchy[edit]

• Cache
  • L0 µOP cache:
    • 2,048 µOPs, 8-way set associative
      • 32-sets, 8-µOP line size
    • Parity protected
  • L1I Cache:
    • 64 KiB 4-way set associative
      • 256-sets, 64 B line size
      • Shared by the two threads, per core
    • Parity protected
  • L1D Cache:
    • 32 KiB 8-way set associative
      • 64-sets, 64 B line size
      • Write-back policy
    • 4-5 cycles latency for Int
    • 7-8 cycles latency for FP
    • SEC-DED ECC
  • L2 Cache:
    • 512 KiB 8-way set associative
    • 1,024-sets, 64 B line size
    • Write-back policy
    • Inclusive of L1
    • 12 cycles latency
    • DEC-TED ECC
  • L3 Cache:
    • Victim cache
    • Summit Ridge, Naples: 8 MiB/CCX, shared across all cores.
    • Raven Ridge: 4 MiB/CCX, shared across all cores.
    • 16-way set associative
      • 8,192-sets, 64 B line size
    • 40 cycles latency
    • DEC-TED ECC
  • System DRAM:
    • 2 channels per die
    • Summit Ridge: up to PC4-21300U (DDR4-2666 UDIMM)
    • Raven Ridge: up to PC4-23466U (DDR4-2933 UDIMM)
    • Naples: up to PC4-21300L (DDR4-2666 RDIMM/LRDIMM)
    • ECC support: x4 DRAM device failure correction (Chipkill), x8 SEC-DED ECC, Patrol and Demand scrubbing, Data poisoning

Zen TLB consists of dedicated level one TLB for instruction cache and another one for data cache.

• TLBs
  • ITLB
    • 8 entry L0 TLB, all page sizes
    • 64 entry L1 TLB, all page sizes
    • 512 entry L2 TLB, no 1G pages
    • Parity protected
  • DTLB
    • 64 entry L1 TLB, all page sizes
    • 1,532-entry L2 TLB, no 1G pages
    • Parity protected

Core[edit]

Pipeline[edit]

Zen+ pipeline is identical to Zen's.

Memory Subsystem[edit]

When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that Zen's L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including EPYC, Ryzen Threadripper, and Zen-based APUs) have an L2 latency of 12 cycles for all access patterns. Only mainstream Zen-based Ryzen processors (i.e., Summit Ridge) have a latency of 17 cycles. The problem has been sorted out with Zen+.

Die[edit]

Zeppelin[edit]

• 12 nm process
• 12 metal layers
• 4,800,000,000 transistors
• ~22.058 mm x ~9.655 mm (Estimated)
• 212.97 mm² die size

Sockets/Platform[edit]

All Zen+-based mainstream consumer microprocessors utilizes AMD's Socket AM4, a unified socket infrastructure. All those processors are a complete system on a chip integrating the northbridge (memory controller) and the southbridge including 16 PCIe lanes for the GPU, 4 PCIe lanes for the NVMe/SATA controllers as well as USB 3.0. The chipset, however, extends the processor with a number of additional connections beyond that offered by the SoC.

StoreMI[edit]

A new feature AMD has added to the 400-series chipset is "StoreMI", a technology with very similar capabilities to Intel's Smart Response Technology which attempts to combine the benefits of fast, but expensive, SSDs along with cheap high-capacity, but slow, HDDs. StoreMI combines the two storage devices into a single virtual drive (single letter drive on Windows) and automatically manages and moves the data across the drives. Essentially, the chipset uses the SSD as a cache for traditional hard drives. The idea is to keep the most recent and most accessed data on the SSD in order to improve real-world responsiveness while keeping the less used data in the slower mechanical hard disk in order to preserve the capacity of the SSD. It’s worth noting that this hierarchy of secondary storage devices can actually extend to main memory. Up to 2 GiB of RAM may be configured and reserved as another level of cache for the HDD on top of the SSD.

All Zen+ Chips[edit]

Bibliography[edit]

• AMD CES Tech Day 2018, Jim Anderson
• AMD CES Tech Day 2018, Lisa Su
• AMD CES Tech Day 2018, Mark Papermaster
• David. S. (August 2018). "AMD Announces Threadripper 2, Chiplets Aid Core Scaling"

Documents[edit]

• AMD Tech Day 2018, Jim Anderson
• AMD Tech Day 2018, Lisa Su
• AMD Tech Day 2018, Mark Papermaster

See Also[edit]

• Intel Coffee Lake