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Difference between revisions of "arm holdings/microarchitectures/cortex-a55"
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|manufacturer 4=SMIC
 
|manufacturer 4=SMIC
 
|introduction=May 29, 2017
 
|introduction=May 29, 2017
−
|process=20 nm
+
|process=16 nm
−
|process 2=16 nm
+
|process 2=14 nm
−
|process 3=14 nm
+
|process 3=10 nm
−
|process 4=10 nm
+
|process 4=7 nm
−
|process 5=
+
|process 5=12 nm
 
|cores=1
 
|cores=1
 
|cores 2=2
 
|cores 2=2
 
|cores 3=3
 
|cores 3=3
 
|cores 4=4
 
|cores 4=4
 +
|cores 9=8
 
|type=In-order
 
|type=In-order
 
|oooe=No
 
|oooe=No
−
|speculative=No
+
|speculative=Yes
−
|renaming=No
+
|renaming=Yes
 
|stages=8
 
|stages=8
 
|decode=2-way
 
|decode=2-way
−
|isa=ARMv8
+
|isa=ARMv8.2
 
|feature=Hardware virtualization
 
|feature=Hardware virtualization
 
|extension=FPU
 
|extension=FPU
Line 31: Line 32:
 
|l1i=8-64 KiB
 
|l1i=8-64 KiB
 
|l1i per=core
 
|l1i per=core
−
|l1i desc=2-way set associative
+
|l1i desc=4-way set associative
 
|l1d=8-64 KiB
 
|l1d=8-64 KiB
 
|l1d per=core
 
|l1d per=core
Line 37: Line 38:
 
|l2=64-256 KiB
 
|l2=64-256 KiB
 
|l2 per=core
 
|l2 per=core
−
|l2 desc=
+
|l2 desc=4-way set associative
 
|l3=0-4 MiB
 
|l3=0-4 MiB
 
|l3 per=Cluster
 
|l3 per=Cluster
 
|predecessor=Cortex-A53
 
|predecessor=Cortex-A53
 
|predecessor link=arm_holdings/microarchitectures/cortex-a53
 
|predecessor link=arm_holdings/microarchitectures/cortex-a53
 +
|successor=Cortex-A510
 +
|successor link=arm_holdings/microarchitectures/cortex-a510
 
}}
 
}}
−
'''Cortex-A55''' is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A725z|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
+
'''Cortex-A55''' (codename '''Ananke''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8.2}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A75|l=arch}}) in {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
  
 
Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
 
== Process Technology ==
 
== Process Technology ==
−
{{empty section}}
+
The Cortex-A55 was primarily designed to make use of [[TSMC]]'s [[16 nm process]] with a [[7 nm]] optimized version set for the end of 2017 or early 2018.
  
 
== Architecture ==
 
== Architecture ==
−
{{empty section}}
+
The Cortex-A55 is an improved version of the A53 which introduces a number of performance enhancements as well as designed to be implemented based on [[ARM Holding|ARM]]'s {{armh|DynamIQ big.LITTLE}} design.
 +
=== Key changes from {{\\|Cortex-A53}} ===
 +
* Higher performance (ARM claims: up to 2x mem perf, up to 15% less power from A53)
 +
* Implements [[ARMv8.2]] (from ARMv8.0)
 +
* Designed as a cluster of [[single-core|1]] to [[8 cores|8]] cores
 +
** Adds DynamIQ Shared Unit (DSU)
 +
* Branch predictor was re-written
 +
* Memory subsystem
 +
** L2
 +
*** L2 cache is now private to each core (from shared between all cores)
 +
*** Latency was cut by half
 +
*** Now runs at the same frequency as the core
 +
*** Configurable size from 64 KiB to 256 KiB
 +
** L3
 +
*** A new L3 cache was introduced
 +
*** Shared by all cores
 +
*** Configurable size: 0 MiB - 4 MiB
 +
* {{arm|NEON}} is improved
 +
** New instructions
 +
** Up to 16x 8-bit [[integer]] operations per cycle
 +
** Up to 8x 16-bit [[floating point]] per cycle
 +
 
 +
== Licensees ==
 +
Arm named the following companies as licensees.
 +
 
 +
{{collist
 +
|count = 3
 +
|
 +
* [[AMD]]
 +
* [[Broadcom]]
 +
* [[HiSilicon]]
 +
* [[STMicroelectronics]]
 +
* [[Samsung]]
 +
* [[MediaTek]]
 +
* [[Huawei]]
 +
* [[Unisoc]]
 +
* [[Amlogic]]
 +
}}
  
 
== Die ==
 
== Die ==

Latest revision as of 03:23, 27 April 2023

Edit Values
Cortex-A55 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC, Samsung, GlobalFoundries, SMIC
IntroductionMay 29, 2017
Process16 nm, 14 nm, 10 nm, 7 nm, 12 nm
Core Configs1, 2, 3, 4
Pipeline
TypeIn-order
OoOENo
SpeculativeYes
Reg RenamingYes
Stages8
Decode2-way
Instructions
ISAARMv8.2
ExtensionsFPU, NEON, TrustZone
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256 KiB/core
4-way set associative
L3 Cache0-4 MiB/Cluster
Succession

Cortex-A55 (codename Ananke) is an ultra-high efficiency microarchitecture designed by ARM Holdings as a successor to the Cortex-A53. The Cortex-A55, which implemented the ARMv8.2 ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on Cortex-A75) in DynamIQ big.LITTLE configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

Process Technology[edit]

The Cortex-A55 was primarily designed to make use of TSMC's 16 nm process with a 7 nm optimized version set for the end of 2017 or early 2018.

Architecture[edit]

The Cortex-A55 is an improved version of the A53 which introduces a number of performance enhancements as well as designed to be implemented based on ARM's DynamIQ big.LITTLE design.

Key changes from Cortex-A53[edit]

  • Higher performance (ARM claims: up to 2x mem perf, up to 15% less power from A53)
  • Implements ARMv8.2 (from ARMv8.0)
  • Designed as a cluster of 1 to 8 cores
    • Adds DynamIQ Shared Unit (DSU)
  • Branch predictor was re-written
  • Memory subsystem
    • L2
      • L2 cache is now private to each core (from shared between all cores)
      • Latency was cut by half
      • Now runs at the same frequency as the core
      • Configurable size from 64 KiB to 256 KiB
    • L3
      • A new L3 cache was introduced
      • Shared by all cores
      • Configurable size: 0 MiB - 4 MiB
  • NEON is improved

Licensees[edit]

Arm named the following companies as licensees.

Die[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

All Cortex-A55 Chips[edit]

 List of all Cortex-A55 Chips
 Main processorIGP
ModelLaunchedDesignerFamilyCoreCTL2$L3$FrequencyMax MemDesignerNameFrequency
10002020MediaTekDimensityCortex-A77, Cortex-A55882.6 GHz
2,600 MHz
2,600,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
Arm HoldingsMali-G77
1000L2020MediaTekDimensityCortex-A77, Cortex-A55882.2 GHz
2,200 MHz
2,200,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
Arm HoldingsMali-G77
800March 2020MediaTekDimensityCortex-A76, Cortex-A55882 GHz
2,000 MHz
2,000,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
Arm HoldingsMali-G57
981025 February 2018Samsung, ARM HoldingsExynosCortex-A55, Meerkat880.25 MiB
256 KiB
262,144 B
2.441406e-4 GiB
, 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
2.704 GHz
2,704 MHz
2,704,000 kHz
, 1.794 GHz
1,794 MHz
1,794,000 kHz
ARM HoldingsMali-G72572 MHz
0.572 GHz
572,000 KHz
9820January 2019Samsung, ARM HoldingsExynosCortex-A75, Cortex-A55, Cheetah880.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
, 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
12 GiB
12,288 MiB
12,582,912 KiB
12,884,901,888 B
0.0117 TiB
ARM HoldingsMali-G76
98252019Samsung, ARM HoldingsExynosCortex-A75, Cortex-A55, Cheetah881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2.73 GHz
2,730 MHz
2,730,000 kHz
, 2.4 GHz
2,400 MHz
2,400,000 kHz
, 1.95 GHz
1,950 MHz
1,950,000 kHz
12 GiB
12,288 MiB
12,582,912 KiB
12,884,901,888 B
0.0117 TiB
ARM HoldingsMali-G76754 MHz
0.754 GHz
754,000 KHz
9902020Samsung, ARM HoldingsExynosMongoose 5, Cortex-A76, Cortex-A55881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
3.016 GHz
3,016 MHz
3,016,000 kHz
, 2.6 GHz
2,600 MHz
2,600,000 kHz
, 2.106 GHz
2,106 MHz
2,106,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
ARM HoldingsMali-G77832 MHz
0.832 GHz
832,000 KHz
G803 February 2020MediaTek, ARM HoldingsHelioCortex-A75, Cortex-A55881.8 GHz
1,800 MHz
1,800,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
ARM HoldingsMali-G52950 MHz
0.95 GHz
950,000 KHz
P6525 June 2019MediaTek, ARM HoldingsHelioCortex-A75, Cortex-A55882 GHz
2,000 MHz
2,000,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
ARM HoldingsMali-G52820 MHz
0.82 GHz
820,000 KHz
P9013 December 2018MediaTek, ARM HoldingsHelioCortex-A75, Cortex-A55882.2 GHz
2,200 MHz
2,200,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
Imagination TechnologiesPowerVR GM 9446970 MHz
0.97 GHz
970,000 KHz
81021 June 2019HiSilicon, ARM HoldingsKirinCortex-A76, Cortex-A55881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.75 MiB
768 KiB
786,432 B
7.324219e-4 GiB
2.27 GHz
2,270 MHz
2,270,000 kHz
, 1.88 GHz
1,880 MHz
1,880,000 kHz
ARM HoldingsMali-G52850 MHz
0.85 GHz
850,000 KHz
98031 August 2018HiSilicon, ARM HoldingsKirinCortex-A76, Cortex-A55882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2.6 GHz
2,600 MHz
2,600,000 kHz
, 1.92 GHz
1,920 MHz
1,920,000 kHz
, 1.8 GHz
1,800 MHz
1,800,000 kHz
ARM HoldingsMali-G76720 MHz
0.72 GHz
720,000 KHz
990 4G6 September 2019HiSilicon, ARM HoldingsKirinCortex-A76, Cortex-A55882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2.86 GHz
2,860 MHz
2,860,000 kHz
, 1.86 GHz
1,860 MHz
1,860,000 kHz
, 2.088 GHz
2,088 MHz
2,088,000 kHz
ARM HoldingsMali-G76600 MHz
0.6 GHz
600,000 KHz
990 5G6 September 2019HiSilicon, ARM HoldingsKirinCortex-A76, Cortex-A55882 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2.86 GHz
2,860 MHz
2,860,000 kHz
, 2.36 GHz
2,360 MHz
2,360,000 kHz
, 1.95 GHz
1,950 MHz
1,950,000 kHz
ARM HoldingsMali-G76600 MHz
0.6 GHz
600,000 KHz
SDM6708 August 2018Qualcomm, ARM HoldingsSnapdragon 600Kryo 360 Gold, Kryo 360 Silver881.7 GHz
1,700 MHz
1,700,000 kHz
, 2.2 GHz
2,200 MHz
2,200,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 615
SDM67522 October 2018Qualcomm, ARM HoldingsSnapdragon 600Kryo 460 Gold, Kryo 460 Silver880.25 MiB
256 KiB
262,144 B
2.441406e-4 GiB
, 0.0625 MiB
64 KiB
65,536 B
6.103516e-5 GiB
2 GHz
2,000 MHz
2,000,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 612
SDM71023 May 2018Qualcomm, ARM HoldingsSnapdragon 700Kryo 360 Gold, Kryo 360 Silver882.2 GHz
2,200 MHz
2,200,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 616500 MHz
0.5 GHz
500,000 KHz
SDM7126 February 2019Qualcomm, ARM HoldingsSnapdragon 700Kryo 360 Gold, Kryo 360 Silver882.3 GHz
2,300 MHz
2,300,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 616550 MHz
0.55 GHz
550,000 KHz
SDM7309 April 2019Qualcomm, ARM HoldingsSnapdragon 700Kryo 470 Gold, Kryo 470 Silver881.8 GHz
1,800 MHz
1,800,000 kHz
, 2.2 GHz
2,200 MHz
2,200,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 618500 MHz
0.5 GHz
500,000 KHz
SDM730G9 April 2019Qualcomm, ARM HoldingsSnapdragon 700Kryo 470 Gold, Kryo 470 Silver882.2 GHz
2,200 MHz
2,200,000 kHz
, 1.8 GHz
1,800 MHz
1,800,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 618575 MHz
0.575 GHz
575,000 KHz
Snapdragon 720G20 January 2020QualcommSnapdragon 700Kryo 465 Gold, Kryo 465 Silver881.8 GHz
1,800 MHz
1,800,000 kHz
, 2.3 GHz
2,300 MHz
2,300,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 618500 MHz
0.5 GHz
500,000 KHz
8cxMarch 2019Qualcomm, ARM HoldingsSnapdragon 800Kryo 495 Gold, Kryo 495 Silver8810 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
, 2.84 GHz
2,840 MHz
2,840,000 kHz
, 3.02 GHz
3,020 MHz
3,020,000 kHz
QualcommAdreno 680 GPU
SDM845February 2018Qualcomm, ARM HoldingsSnapdragon 800Kryo 385 Gold, Kryo 385 Silver881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
10 GiB
10,240 MiB
10,485,760 KiB
10,737,418,240 B
0.00977 TiB
QualcommAdreno 630 GPU710 MHz
0.71 GHz
710,000 KHz
SDM8505 June 2018QualcommSnapdragon 800Kryo 385 Gold, Kryo 385 Silver881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2.96 GHz
2,960 MHz
2,960,000 kHz
8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
0.00781 TiB
QualcommAdreno 630
SDM855March 2019ARM Holdings, QualcommSnapdragon 800Kryo 485 Gold, Kryo 485 Silver880.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
, 0.75 MiB
768 KiB
786,432 B
7.324219e-4 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
, 2.42 GHz
2,420 MHz
2,420,000 kHz
, 2.84 GHz
2,840 MHz
2,840,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
QualcommAdreno 640 GPU257 MHz
0.257 GHz
257,000 KHz
SDM855ACMarch 2019Qualcomm, ARM HoldingsSnapdragon 800Kryo 485 Gold, Kryo 485 Silver881 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
, 0.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
1.8 GHz
1,800 MHz
1,800,000 kHz
, 2.42 GHz
2,420 MHz
2,420,000 kHz
, 2.96 GHz
2,960 MHz
2,960,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
QualcommAdreno 640 GPU250 MHz
0.25 GHz
250,000 KHz
SDM865March 2020Qualcomm, ARM HoldingsSnapdragon 800Kryo 585 Gold, Kryo 585 Silver, kryo 585 prime880.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
, 0.75 MiB
768 KiB
786,432 B
7.324219e-4 GiB
2.42 GHz
2,420 MHz
2,420,000 kHz
, 2.84 GHz
2,840 MHz
2,840,000 kHz
, 2.11 GHz
2,110 MHz
2,110,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
QualcommAdreno 650 GPU257 MHz
0.257 GHz
257,000 KHz
Count: 27
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a55&oldid=101603"
Facts about "Cortex-A55 - Microarchitectures - ARM"
RDF feed
codenameCortex-A55 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a55 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +, Samsung +, GlobalFoundries + and SMIC +
microarchitecture typeCPU +
nameCortex-A55 +
pipeline stages8 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +