• intel/mcs-4/4004
  |package 0 pitch=2.54 mm |package 1 pitch=2.3 mm
  5 KB (748 words) - 21:37, 21 November 2021
• 10 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch
  2 KB (177 words) - 23:04, 20 May 2018
• 6 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch
  1 KB (119 words) - 23:04, 20 May 2018
• 1.5 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  3 KB (332 words) - 23:04, 20 May 2018
• 1 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch (M1P)
  1 KB (166 words) - 23:04, 20 May 2018
• 800 nm lithography process
  ...and early 1990s. A '''"0.8 µm process"''' refers to a process which has a gate length of 0.8 µm. This process was later replaced by [[650 nm]], [[600 nm] |Gate Length
  3 KB (272 words) - 23:04, 20 May 2018
• technology node
  ...a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading fou ...nsity doubling, the [[contacted poly pitch]] (CPP) and the [[minimum metal pitch]] (MMP) need to scale by roughly 0.7x each node. In other words, a scaling
  8 KB (1,225 words) - 13:48, 14 December 2022
• 32 nm lithography process
  | process 1 gate len = 30 nm | process 1 gate len Δ =  
  10 KB (1,090 words) - 19:14, 8 July 2021
• 14 nm lithography process
  ...on of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and has been replaced by the [[ | process 1 fin pitch = 42 nm
  17 KB (2,243 words) - 19:32, 25 May 2023
• 45 nm lithography process
  ...Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-volume manufacturing process. |Contacted Gate Pitch
  5 KB (602 words) - 05:51, 20 July 2018
• intel/microarchitectures/bonnell
  ...is the first high-volume manufacturing process to introduce High-k + metal gate transistors. | Gate Pitch || 180 nm
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/broadwell (client)
  ...[[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.0706 µm² and 0.0499 µm² for high perfo | Fin Pitch || 60 nm || 42 || 0.70x
  14 KB (1,891 words) - 14:37, 6 January 2022
• 20 µm lithography process
  |Contacted Gate Pitch |Interconnect Pitch
  902 bytes (119 words) - 23:04, 20 May 2018
• 22 nm lithography process
  ...on of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 22 nm process began ...ransistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new pro
  7 KB (891 words) - 09:52, 25 November 2020
• 16 nm lithography process
  ...on of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with [[10 nm lithography process|10 | process 1 fin pitch = 48 nm
  4 KB (580 words) - 17:00, 26 March 2019
• 20 nm lithography process
  ...on of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 20 nm process began | process 1 gate len =  
  4 KB (483 words) - 23:04, 20 May 2018
• intel/microarchitectures/ivy bridge (client)
  ...hancements. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products. ...eneration of [[FinFET]]. This correlates to 8 nm Fin width and a 60 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high perfor
  5 KB (689 words) - 13:44, 2 May 2020
• intel/microarchitectures/westmere (client)
  ...oyed a roughly 0.7x scaling compared to the [[45 nm process]] for the gate pitch and metal 1 interconnect. ! !! Nehalem !! Westmere !! Δ !! rowspan="7" | [[File:intel 32nm gate.png|250px]]
  10 KB (1,258 words) - 21:07, 9 March 2018
• intel/microarchitectures/nehalem (client)
  ...is the first high-volume manufacturing process to introduce High-k + metal gate transistors. ! !! Core !! Nehalem !! Δ !! rowspan="7" | [[File:intel 45nm gate.png|250px]]
  4 KB (459 words) - 21:44, 26 December 2023
• intel/microarchitectures/p6
  | Contacted Gate Pitch​ || 550 nm || 500 nm || 0.91x | Interconnect Pitch || 880 nm || 640 nm || 0.73x
  3 KB (325 words) - 21:34, 22 February 2020

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