Page title matches

• 16 nm FinFET process
  39 bytes (4 words) - 12:23, 13 June 2018

Page text matches

• WikiChip
  rect 816 29 1061 162 [[XXXXXXXXX|FinFET Transistor]]
  4 KB (394 words) - 12:00, 13 February 2020
• mosfet
  {{see also|FinFET}} [[file:FINFET MOSFET.png|thumb|upright=1.2|A [[FinFET]] (fin field-effect transistor), a type of [[multi-gate MOSFET]].]]
  193 KB (26,852 words) - 19:51, 11 March 2025
• cmos
  ...Application, Forecast Analysis |url=https://financialplanning24.com/global-finfet-technology-market-2024-growth-analysis-by-manufacturers-regions-type-and-ap
  39 KB (5,297 words) - 20:00, 11 March 2025
• technology node
  ...length remained more or less a constant. This is due to the properties of FinFET; for example the effective channel length is a function of the new fins (<c
  13 KB (1,896 words) - 09:30, 20 April 2025
• 14 nm lithography process
  ...has reached very healthy numbers. 14 nm became [[Intel]]'s 2nd generation FinFET transistors. Intel uses TiN pMOS / TiAlN nMOS as work function metals. Inte {{finfet nodes comp
  18 KB (2,283 words) - 20:34, 19 March 2025
• intel/microarchitectures/broadwell (client)
  Broadwell is designed to be manufactured using [[14 nm]] Tri-gate [[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (sho
  15 KB (1,935 words) - 19:08, 5 April 2025
• 22 nm lithography process
  The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process bec {{finfet nodes comp
  7 KB (891 words) - 09:52, 25 November 2020
• 16 nm lithography process
  {{finfet nodes comp ...inFET</info>, 16FF+ <info>16nm FinFET Plus</info>, 16FFC, 12FFC <info>12nm FinFET Compact</info>, 12FFN
  4 KB (582 words) - 15:50, 17 April 2025
• intel/microarchitectures/ivy bridge (client)
  ...m]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a 60 nm Fin pitch (shown below). S
  5 KB (691 words) - 08:03, 13 October 2024
• 10 nm lithography process
  ...17-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 30-40s nm [[fin pitches]]. Those nodes typically have Samsung demonstrated their 128 Megabit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-lit
  16 KB (2,146 words) - 19:35, 27 June 2025
• 7 nm lithography process
  ...e, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pi ...the company has had previously. To that end, this is a fourth-generation [[FinFET]], fifth-generation [[HKMG]], gate-last, dual gate oxide process.
  16 KB (2,317 words) - 19:45, 27 June 2025
• 5 nm lithography process
  ...e, the 5-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 20s of nanometer and densest metal pi The N5 node continues to use [[bulk silicon]] [[FinFET transistors]]. Leveraging their experience from 7+, [[5 nm]] makes extensiv
  17 KB (2,316 words) - 18:00, 21 March 2025
• mediatek/helio/mt6799
  * Mair, Hugh, et al. "3.4 A 10nm FinFET 2.8 GHz tri-gear deca-core CPU complex with optimized power-delivery networ
  4 KB (549 words) - 16:22, 29 December 2018
• ibm/microarchitectures/power9
  ...on [[GlobalFoundries]]'s High-Performance [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM a * GlobalFoundries [[14 nm process|14 nm FinFET on SOI Process]]
  14 KB (1,915 words) - 11:21, 18 April 2025
• 3 nm lithography process
  {{finfet nodes comp | process 1 transistor = FinFET
  10 KB (1,206 words) - 19:15, 27 June 2025
• intel/process
  | FinFET || Optimized <br>FinFET || Optimized <br>FinFET || Optimized <br>FinFET || RibbonFET || Optimized <br>RibbonFET || TBD || TBD ....png|250px|thumb|Intel's fab roadmap from 2003 <!-- Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics
  15 KB (2,337 words) - 15:00, 4 April 2025
• ibm/microarchitectures/z14
  ...are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process featuring highly-dense [[deep tren ** CMOS FinFET SOI
  8 KB (1,204 words) - 14:02, 23 September 2019
• renesas/r-car/h3
  * [[16 nm process]], CMOS FinFET * Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−
  4 KB (571 words) - 15:43, 29 December 2018
• renesas/r-car/h3 (sip)
  * [[16 nm process]], CMOS FinFET * Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−
  4 KB (495 words) - 16:32, 13 December 2017
• apple/ax
  | "[[10 nm]]"<br>[[TSMC]] FinFET
  12 KB (1,577 words) - 07:49, 23 April 2025

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