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39 bytes (4 words) - 12:23, 13 June 2018
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- rect 816 29 1061 162 [[XXXXXXXXX|FinFET Transistor]]4 KB (394 words) - 12:00, 13 February 2020
- ...length remained more or less a constant. This is due to the properties of FinFET; for example the effective channel length is a function of the new fins (<c8 KB (1,225 words) - 13:48, 14 December 2022
- {{finfet nodes comp | process 1 transistor = FinFET17 KB (2,243 words) - 19:32, 25 May 2023
- Broadwell is designed to be manufactured using [[14 nm]] Tri-gate [[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (sho14 KB (1,891 words) - 14:37, 6 January 2022
- The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process bec {{finfet nodes comp7 KB (891 words) - 09:52, 25 November 2020
- {{finfet nodes comp ...FinFET</info>, 16FF+<info>16nm FinFET Plus</info>, 16FFC, 12FFC<info>12nm FinFET Compact</info>, 12FFN4 KB (580 words) - 17:00, 26 March 2019
- ...m]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a 60 nm Fin pitch (shown below). S5 KB (689 words) - 13:44, 2 May 2020
- ...17-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 30-40s nm [[fin pitches]]. Those nodes typically have | process 1 transistor = FinFET14 KB (1,903 words) - 06:52, 17 February 2023
- ...e, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pi ...the company has had previously. To that end, this is a fourth-generation [[FinFET]], fifth-generation [[HKMG]], gate-last, dual gate oxide process.13 KB (1,941 words) - 02:40, 5 November 2022
- ...e, the 5-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 20s of nanometer and densest metal pi The N5 node continues to use [[bulk silicon]] [[FinFET transistors]]. Leveraging their experience from 7+, 5 nm makes extensive us11 KB (1,662 words) - 02:58, 2 October 2022
- * Mair, Hugh, et al. "3.4 A 10nm FinFET 2.8 GHz tri-gear deca-core CPU complex with optimized power-delivery networ4 KB (549 words) - 16:22, 29 December 2018
- ...on [[GlobalFoundries]]'s High-Performance [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM a * GlobalFoundries [[14 nm process|14 nm FinFET on SOI Process]]14 KB (1,905 words) - 23:38, 22 May 2020
- {{finfet nodes comp | process 1 transistor = FinFET5 KB (565 words) - 15:58, 22 July 2024
- ...2003.png|250px|thumb|Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.13 KB (1,998 words) - 03:56, 4 March 2022
- ...are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process featuring highly-dense [[deep tren ** CMOS FinFET SOI8 KB (1,204 words) - 14:02, 23 September 2019
- * [[16 nm process]], CMOS FinFET * Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−4 KB (571 words) - 15:43, 29 December 2018
- * [[16 nm process]], CMOS FinFET * Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−4 KB (495 words) - 16:32, 13 December 2017
- Lujiazui is manufactured on [[TSMC]]'s [[16 nm|16 nm FinFET process]]. * [[16 nm|16 nm FinFET]] (from [[28 nm]])2 KB (313 words) - 12:10, 12 December 2019
- * [[14 nm process]] ([[FinFET]])13 KB (1,962 words) - 14:48, 21 February 2019
- ...fabricated on Samsung's [[10 nm process|10nm]] EUV (Extreme Ultra Violet) FinFET process and features [[8 cores]] in a dual-cluster configuration consisting5 KB (713 words) - 07:19, 16 May 2024