• mips/mips32 instruction set
  ** [[#Branch instructions|Branch Instructions]] ** [[#Branch instructions|Branch Instructions]]
  18 KB (2,445 words) - 08:24, 9 November 2019
• mirc/regex
  | start of alternative branch
  27 KB (4,356 words) - 20:17, 29 June 2021
• amd/am2900
  | {{\|AM29803A}} || 16-way branch control unit for use with {{\|AM2909A}} || 16
  9 KB (1,061 words) - 22:55, 18 June 2019
• boolean algebra
  ...ean algebra''' (or less commonly '''symbolic logic''') is a [[instance of::branch of algebra]] that deals with only two logic values - [[0]] (corresponding t
  32 KB (5,239 words) - 01:23, 19 May 2016
• Property:instance of
  ** [[allows value::branch of algebra]]
  2 KB (189 words) - 13:28, 11 August 2018
• intel/microarchitectures/bonnell
  ===== Branch predictor ===== ...able has 4096 entries and is [[competitively shared]] between threads. The branch buffer target has 128 entries (4-way by 32 sets). While [[unconditional jum
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  * Double the size of the branch prediction history table === Branch Prediction ===
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  ...al-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchi ...ction of out-of-order execution, silvermont's more aggressive fetching and branch prediction mean stalled instructions do not clog the entire pipeline as it
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/haswell (client)
  ...which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public. ...heduler resources get allocated as well - this includes stores, loads, and branch buffer entries. Note that due to how dependencies are handled, there may be
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  *** Redesigned branch prediction ...ont-end of Sandy Bridge is the entirely new [[µOP cache]], the overhauled branch predictor and further decoupling of the front-end, and the improved macro-o
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  *** Improved [[branch prediction unit]] ...ream than in previous architectures. The intimate improvements done in the branch predictor were not further disclosed by Intel.
  79 KB (11,922 words) - 06:46, 11 November 2022
• exponential technology/x704
  ...ger or floating point, but not both), a single load/store operation, and a branch instruction.
  8 KB (1,228 words) - 20:49, 2 June 2019
• intel/microarchitectures/coffee lake
  <tr><td>Branch</td></tr>
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/k6
  * Branch Predictor ** 2-level predictor with 8192 entry branch history table
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/k9
  ...ribed by Alsup as: "K9 fetched 8 instructions every other cycle and made 2 branch predictions associated with 3 next fetch addresses every other cycle. K9 is
  2 KB (287 words) - 17:28, 1 December 2018
• amd/microarchitectures/zen
  ** Branch Predictor *** Improved branch mispredictions
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  *** Improved [[branch prediction unit]] ...operation, the front-end throughput was improved. AMD reported that the [[branch prediction unit]] has been reworked. This includes improvements to the [[pr
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  ...VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread). ...le of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscel
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread). ...le of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscel
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  * Improved branch prediction ! Fetch/Branch || Slices issue VSU & AGEN || VSU Pipe || LSU Slices
  14 KB (1,905 words) - 23:38, 22 May 2020
• qualcomm/microarchitectures/falkor
  **** 3 instructions + 1 direct branch per cycle
  6 KB (822 words) - 13:01, 19 May 2021
• phytium/microarchitectures/xiaomi
  ...erscalar]], [[out-of-order]], 4-decode/4-dispatch pipeline with a hybrid [[branch prediction]]. ...required for retrieval of instructions from the L1. Xiaomi has a hybrid [[branch predictor]] made of a [[TAGE predictor]] and a 512-entry [[indirect predict
  7 KB (940 words) - 00:12, 8 March 2021
• amd/ryzen 7
  ...) through doubling of the L3 cache, 2x wider FPU datapath, and an improved branch prediction unit. Zen 2 also provided modest clock frequency improvements ov
  15 KB (2,095 words) - 12:18, 2 October 2022
• amd/ryzen 5
  ...) through doubling of the L3 cache, 2x wider FPU datapath, and an improved branch prediction unit. Zen 2 also provided modest clock frequency improvements ov
  14 KB (1,864 words) - 07:09, 7 October 2020
• amd/microarchitectures/zen 3
  *** Increased branch prediction bandwidth *** "zero-bubble" branch prediction
  15 KB (1,978 words) - 22:13, 6 April 2023
• loongson/godson 2
  ...speeds (doubling with each model) along with a larger cache and improved [[branch predictor]]s for triple the performance improvement each time. With the int
  6 KB (710 words) - 17:11, 11 April 2017
• loongson/godson 2/2c
  ...and almost twice the frequency as the {{\\|2B}}, along with an improved [[branch predictor]].
  4 KB (418 words) - 16:31, 13 December 2017
• intel/microarchitectures/merced
  * Branch Predictor ** Indirect branches handled with 64 entry Multiway Branch Prediction Table
  7 KB (978 words) - 21:16, 20 January 2021
• macro-operation fusion
  ...tional [[jump instruction]]. The produced output is a single operation-and-branch instruction. The final fused instruction remains as such for its remaining
  11 KB (1,614 words) - 23:01, 8 May 2020
• arm holdings/microarchitectures/cortex-a55
  * Branch predictor was re-written
  4 KB (603 words) - 04:23, 27 April 2023
• compaq/microarchitectures/alpha 21464
  * Seznec, André, et al. "Design tradeoffs for the Alpha EV8 conditional branch predictor." Computer Architecture, 2002. Proceedings. 29th Annual Internati
  2 KB (228 words) - 13:20, 31 March 2019
• arm/26-bit architectures
  ...Consequently, <code>B</code> and <code>BL</code> signed 24-bit offsets can branch to any address.
  3 KB (535 words) - 09:13, 18 February 2021
• arm/armv1
  * [[#branch_instructions|Branch Instructions]] ...=<span id="branch_instructions">'''Branch Instructions'''</span><br><small>Branch instructions order instruction processing to start elsewhere conditionally
  10 KB (1,558 words) - 15:07, 2 July 2017
• arm holdings/microarchitectures/arm6
  ...e registers, it's no longer possible to automatically save those bits on a branch and link instruction execution. Upon an exception, however, the CPSR gets c
  11 KB (1,679 words) - 18:49, 18 May 2023
• x86/avx-512
  ...r|CF|Carry Flag}} (less than), and {{abbr|PF|Parity Flag}} (unordered) for branch instructions. UCOMI instructions perform an unordered compare and only gene ...nd source2, sets the {{abbr|ZF|Zero Flag}} and {{abbr|CF|Carry Flag}} (for branch instructions) to indicate if the respective result is all zeros.
  83 KB (13,667 words) - 15:45, 16 March 2023
• ibm/microarchitectures/z14
  ** Faster branch wakeup * '''IFB''' - Instruction fetch and branch prediction
  8 KB (1,204 words) - 14:02, 23 September 2019
• intel/microarchitectures/skylake (server)
  <tr><td>Branch</td></tr>
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  *** Enhanced branch prediction *** Supports faster branch redirection.
  9 KB (1,128 words) - 13:28, 17 July 2023
• pezy/pezy-scx
  ...witching done to reduce [[forwarding]] and in order mitigate the lack of [[branch prediction]]. Explicit switching of active threads is also done in order to
  6 KB (838 words) - 09:33, 9 May 2019
• mirc/identifiers/$iif
  ...condition. Because the conditional was $false, the $custom1 alias in the T branch is not called.
  3 KB (481 words) - 05:39, 4 April 2020
• intel/microarchitectures/whiskey lake
  ...ting with stepping 11. Stepping 12 adds hardware support for mitigation of Branch Target Injection (Spectre V2) and Speculative Store Bypass.
  5 KB (650 words) - 03:47, 9 January 2020
• zhaoxin/microarchitectures/wudaokou
  ** Branch prediction unit was reworked and optimized
  9 KB (1,134 words) - 13:02, 17 June 2019
• cve/cve-2017-5753
  ...is (Variant 1) vulnerability by making the microprocessor take the wrong [[branch target]]. ...code segment is identified, the attacker can then train the processor's [[branch predictor]] that the bounds check will likely be true. This is done by repe
  12 KB (1,869 words) - 10:01, 27 February 2019
• cve/cve-2017-5715
  ...rmation to the attacker that wouldn't normally be exposed due to a wrong [[branch target]] being temporarily chosen, resulting in {{cve|cve-2017-5753|Spectre ...nformation than intended. This method influences the [[indirect branch]] [[branch predictor|predictor]] in the microprocessor to [[speculative execution|spec
  7 KB (943 words) - 09:59, 27 February 2019
• spectre
  ** {{cve|CVE-2017-5715}}, Spectre, Variant 2, Branch Target Injection
  213 bytes (24 words) - 16:54, 26 January 2018
• samsung/microarchitectures/m1
  ** Advanced [[branch predictor]] There are two pipeline stages for the branch predictor for generating addresses. There are three cycles for [[instructio
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  *** Larger branch prediction * branch misprediction penalty increased (16 cycles, from 14)
  20 KB (3,149 words) - 10:44, 15 February 2020
• mirc/identifiers/$regerrstr
  * 54: DEFINE group contains more than one branch
  5 KB (685 words) - 18:31, 21 December 2020
• movidius/microarchitectures/shave v2.0
  * [[Branch delay slots]] The '''branch and repeat unit''' ('''BRU''') is another execution unit with the ability t
  12 KB (1,749 words) - 19:05, 20 January 2021
• intel/microarchitectures/tremont
  ** Improved [[branch predictor]]
  3 KB (428 words) - 19:12, 10 December 2020

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