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- | package = FCLGA-1366 | package 2 = FCBGA-136443 KB (5,739 words) - 21:30, 22 April 2024
- |package = PDIP-28, VQFN-28, QFN-32, TQFP-32, MLF-32 ...ight|The ATMEGA328P-PU - The ATmega 328 in a 28-pin [[plastic dual-in-line package]].]]2 KB (219 words) - 23:43, 17 December 2013
- |package = 16-pin [[Dual in-line package|DIP]] ...compatible with the [[Intel 4004]]. The chip came in 16-pin [[Dual in-line package|DIP]] packages. The HD35404 was part of the [[Hitachi HMCS-4]], an [[Intel1 KB (157 words) - 01:34, 24 December 2015
- | package = DIP40 | package 2 = FP429 KB (1,061 words) - 22:55, 18 June 2019
- | package = <!-- package, e.g. "DIP16" --> | package 2 = <!-- package, e.g. "DIP16" -->4 KB (462 words) - 19:14, 13 October 2019
- | package = DIP16 | package 2 = DIP206 KB (685 words) - 22:49, 5 February 2016
- | package = | package 2 =4 KB (521 words) - 14:38, 11 June 2017
- | desc 6 = Package Designation * '''Package Designation'''7 KB (851 words) - 20:53, 29 July 2021
- | package = DIP16 ...s were packaged in 16-pin ceramic [[Dual in-line package|DIP]]. The 16-pin package, which proved to be the most problematic restriction was imposed by manage4 KB (433 words) - 22:40, 27 June 2019
- |package module 1={{packages/intel/fcbga-1356}} ...urst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (596 words) - 16:15, 13 December 2017
- |package module 1={{packages/intel/fcbga-1356}} ...urst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (596 words) - 16:15, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...MHz and a turbo frequency of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (627 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 memory.4 KB (627 words) - 16:20, 13 December 2017
- |package module 1={{packages/intel/fcbga-1356}} ...rst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (640 words) - 02:21, 16 January 2019
- |package module 1={{packages/intel/fcbga-1356}} ...burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (650 words) - 02:21, 16 January 2019
- | package 0 = FCBGA-1168 | package 0 type = FCBGA5 KB (469 words) - 16:22, 13 December 2017
- |package module 1={{packages/intel/fcbga-1364}} The '''Intel Core i5-5350H''' is a [[dual core]] [[64-bit architecture|64-bit]] [[microprocessor]] introduced by [[In4 KB (415 words) - 16:19, 13 December 2017
- |package module 1={{packages/intel/fcbga-1356}} ...burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6167U comes with an additional 64 MiB of [[em4 KB (631 words) - 16:18, 13 December 2017
- |package module 1={{packages/intel/fcbga-1356}} ...urst frequency of 1.1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6287U comes with an additional 64 MiB of [[em4 KB (649 words) - 16:20, 13 December 2017
- | package 0 = FCBGA-576 | package 0 type = FCBGA3 KB (323 words) - 16:10, 13 December 2017
- | package = FCBGA-437 | package 2 = PBGA-44117 KB (2,292 words) - 09:32, 16 July 2019
- | package = | package type =4 KB (424 words) - 16:15, 13 December 2017
- * 533 MT/s dual mode ([[gunning transceiver logic|GTL]] & [[CMOS]]) [[front side bus|FSB]] ...pipeline. The pipeline is shown below. Note the pipeline is duplicated for dual-issue execution.38 KB (5,468 words) - 20:29, 23 May 2019
- | package = FCBGA1170 ...troduced by [[Intel]] in 2009 after replacing the previous {{intel|Pentium Dual-Core}} family.20 KB (2,661 words) - 00:45, 11 October 2017
- | package = FCBGA1170 ...turbo boost is generally not significant or present, and most Celerons are dual-core only. They also lack helpful features like hyper-threading, and have g25 KB (3,201 words) - 03:13, 22 September 2018
- |package=FCBGA1170 |package type=FCBGA4 KB (544 words) - 17:43, 27 March 2018
- |package=FCBGA1170 |package type=FCBGA4 KB (580 words) - 09:40, 8 July 2022
- |package=FCBGA1170 |package type=FCBGA4 KB (539 words) - 17:39, 27 March 2018
- |package=FCBGA1170 |package type=FCBGA5 KB (722 words) - 01:50, 24 November 2018
- |package=FCBGA1170 |package type=FCBGA4 KB (539 words) - 17:39, 27 March 2018
- | package = fcBGA-1667 * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/D13 KB (1,784 words) - 08:04, 6 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (593 words) - 02:17, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (593 words) - 02:18, 1 April 2019
- |package name 1=intel,fcbga_1667 ...]. It operates at 2.2 GHz with a TDP of 35 W and supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (582 words) - 02:21, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (596 words) - 02:18, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:16, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:16, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (593 words) - 02:17, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.3 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:16, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (596 words) - 02:17, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (595 words) - 09:36, 14 May 2021
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (595 words) - 02:16, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:18, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.4 KB (595 words) - 02:16, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (595 words) - 02:17, 1 April 2019
- |l4 per=package | Broadwell EP || BDW-EP || {{intel|Xeon E5}}, Dual-Processor platform14 KB (1,891 words) - 14:37, 6 January 2022
- |l4 per=package *** Per package27 KB (3,750 words) - 06:57, 18 November 2023
- ==== Entire SoC Overview (dual) ==== [[File:sandy bridge soc block diagram (dual).svg|800px]]84 KB (13,075 words) - 00:54, 29 December 2020
- |side cache per=package ...tyle="text-align: left;" | Entry-level Budget || rowspan="2" | [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}79 KB (11,922 words) - 06:46, 11 November 2022
- |side cache per=package ...Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}38 KB (5,431 words) - 10:41, 8 April 2024
- * Package ...chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PC23 KB (3,613 words) - 12:31, 20 June 2021
- |package module 1={{packages/intel/pga-988b}} |package=rPGA9985 KB (710 words) - 16:24, 13 December 2017
- |package module 1={{packages/intel/pga-988b}} |package=rPGA9985 KB (710 words) - 03:49, 26 June 2018
- |package module 1={{packages/intel/fcbga-1356}} ...rst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6650U comes with an additional 64 MiB of [[em4 KB (649 words) - 16:22, 13 December 2017
- |package module 1={{packages/intel/fcbga-1356}} ...rst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6660U comes with an additional 64 MiB of [[em4 KB (649 words) - 16:22, 13 December 2017
- |package module 1={{packages/intel/fcbga-1356}} ...rst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (654 words) - 17:22, 26 March 2018
- |package module 1={{packages/intel/lga-1151}} ...GHz. The E3-1280 v5 has a [[TDP]] of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (485 words) - 00:29, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...f 4 GHz. The E3-1275 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[int4 KB (620 words) - 00:27, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...f 4 GHz. The E3-1270 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (490 words) - 00:29, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...special low-power chip with a TDP of 45 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (489 words) - 16:26, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...3.9 GHz. The E3-1245 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[int4 KB (609 words) - 00:29, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...Hz. The E3-1240L v5 has a [[TDP]] of 25 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (484 words) - 16:26, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (490 words) - 00:29, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...special low-power chip with a TDP of 25 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[int4 KB (608 words) - 16:26, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...r full load, is in the range of 45 - 55 Watts. It supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (506 words) - 00:29, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...GHz. The E3-1225 V5 has a [[TDP]] of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[int4 KB (620 words) - 00:24, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...GHz. The E3-1220 v5 has a [[TDP]] of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]3 KB (490 words) - 00:29, 7 April 2018
- |package module 1={{packages/intel/lga-1151}} ...n ultra low power chip with a TDP of 35 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[int4 KB (624 words) - 00:27, 7 April 2018
- |package module 1={{packages/intel/fcbga-1440}} ...350 MHz with a turbo frequency of 1.05 GHz. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (648 words) - 16:27, 13 December 2017
- |package module 1={{packages/intel/fcbga-1440}} ...350 MHz with a turbo frequency of 1.05 GHz. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (646 words) - 05:24, 14 July 2018
- |package module 1={{packages/intel/fcbga-1440}} ...corporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (654 words) - 16:27, 13 December 2017
- |package module 1={{packages/intel/fcbga-1440}} ...corporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (654 words) - 16:27, 13 December 2017
- |package module 1={{packages/intel/fcbga-1440}} ...corporating 128 MiB of [[eDRAM]] on-package. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (663 words) - 16:27, 13 December 2017
- |package module 1={{packages/intel/fcbga-1440}} ...at 350 MHz with a turbo frequency of 1 GHz. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (640 words) - 16:27, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...MHz and a turbo frequency of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (607 words) - 16:25, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (610 words) - 16:25, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...MHz and a turbo frequency of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (616 words) - 16:25, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...350 MHz and a turbo frequency of 1 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (623 words) - 06:18, 5 November 2020
- |package module 1={{packages/intel/lga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (610 words) - 16:25, 13 December 2017
- |package module 1={{packages/intel/lga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (606 words) - 16:25, 13 December 2017
- |package name 1=intel,fcbga_1515 ...hics 515}} [[IGP]] operating at up to 800 MHz and supports up to 16 GiB of dual-channel DDR3-1866 memory.4 KB (581 words) - 17:57, 28 August 2018
- |package module 1={{packages/intel/fcbga-1356}} ...urst frequency of 950 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (597 words) - 16:25, 13 December 2017
- |package name 1=intel,fcbga_1667 ...s]]. It operates at 1.3 GHz with a TDP of 20 W supporting up to 128 GiB of dual-channel DDR4-1600 memory.4 KB (613 words) - 02:20, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.2 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (596 words) - 02:16, 1 April 2019
- |package name 1=intel,fcbga_1667 ...ost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.4 KB (596 words) - 02:16, 1 April 2019
- | package = FCBGA-1234 | package type = FCBGA6 KB (626 words) - 19:52, 6 October 2020
- | package = FCBGA-1234 | package type = FCBGA6 KB (603 words) - 16:24, 13 December 2017
- | package = FCBGA-1234 | package type = FCBGA6 KB (601 words) - 16:24, 13 December 2017
- | package = FCBGA-1234 | package type = FCBGA6 KB (603 words) - 16:24, 13 December 2017
- | package = FCBGA-1234 | package type = FCBGA6 KB (623 words) - 16:24, 13 December 2017
- | package = FCBGA-1234 | package type = FCBGA6 KB (623 words) - 16:24, 13 December 2017
- | package = FCBGA-1234 | package type = FCBGA6 KB (627 words) - 16:24, 13 December 2017
- |package name 1=intel,fcbga_1515 '''Core M7-6Y75''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MP4 KB (613 words) - 17:58, 28 August 2018
- |package name 1=intel,fcbga_1515 '''Core M5-6Y54''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MP4 KB (613 words) - 17:58, 28 August 2018
- |package name 1=intel,fcbga_1515 '''Core M5-6Y57''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MP4 KB (613 words) - 17:58, 28 August 2018
- |package name 1=intel,fcbga_1515 '''Core M3-6Y30''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MP4 KB (613 words) - 17:58, 28 August 2018
- |package module 1={{packages/intel/fcbga-1356}} ...burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.4 KB (616 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...MHz and a turbo frequency of 1.15 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (609 words) - 16:18, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (618 words) - 16:18, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...350 MHz and a turbo frequency of 1 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (612 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...MHz and a turbo frequency of 1.15 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (611 words) - 16:18, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...MHz and a turbo frequency of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (615 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (615 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fcbga-1440}} ...t 350 MHz with a turbo frequency of 950 MHz. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (613 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fcbga-1440}} ...t 350 MHz with a turbo frequency of 900 MHz. This model supports 64 GiB of dual-channel DDR4-2133 memory.4 KB (613 words) - 02:11, 16 January 2019
- |package module 1={{packages/intel/fcbga-1440}} ...t 350 MHz with a turbo frequency of 950 MHz. This model supports 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (613 words) - 16:17, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (609 words) - 16:16, 13 December 2017
- |package module 1={{packages/intel/fclga-1151}} ...0 MHz and a turbo frequency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.4 KB (606 words) - 16:16, 13 December 2017
- | package = FCLGA-1168 | package 1 = FCLGA-115125 KB (3,397 words) - 03:12, 3 October 2022
- | package = FCBGA-1440 | package 2 = FCBGA-136434 KB (4,663 words) - 20:38, 20 February 2023
- | package 0 = FCBGA-676 | package 0 type = FCBGA8 KB (1,031 words) - 14:09, 10 May 2019
- | package = *** Dual-ported RAM, single-cycle access5 KB (596 words) - 21:23, 19 November 2017
- |l4 per=package ...eleron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes30 KB (4,192 words) - 13:48, 10 December 2023
- |package name 1=amd,fp6 ...llers, each supporting DDR4 or LPDDR4x. This chip supports up to 64 GiB of dual-channel DDR4 memory with data rates of up to 3200 MT/s (51.2 GB/s) or up to5 KB (745 words) - 00:23, 26 March 2023
- |package name 1=amd,fp6 ...llers, each supporting DDR4 or LPDDR4x. This chip supports up to 64 GiB of dual-channel DDR4 memory with data rates of up to 3200 MT/s (51.2 GB/s) or up to5 KB (748 words) - 00:43, 26 March 2023
- |package name 1=amd,fp6 ...llers, each supporting DDR4 or LPDDR4x. This chip supports up to 64 GiB of dual-channel DDR4 memory with data rates of up to 3200 MT/s (51.2 GB/s) or up to5 KB (748 words) - 00:51, 26 March 2023
- |package module 1={{packages/intel/fcbga-1356}} ...base frequency of 2.4 GHz with a TDP of 15 Watts, supports up to 32 GiB of dual-channel DDR4-2133. The i3-7100U incorporates Intel's {{intel|HD Graphics 624 KB (626 words) - 16:18, 13 December 2017
- |package name 1=intel,fcbga_1515 ...Turbo Boost}} frequency of 2.6 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's {{intel|HD Grap4 KB (654 words) - 17:58, 28 August 2018
- |package name 1=intel,fcbga_1515 ...ncy of 3.6 GHz for a single active core. This MPU supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's {{intel|HD Grap4 KB (660 words) - 18:04, 28 August 2018
- |package module 1={{packages/intel/fcbga-1356}} ...ncy of 3.5 GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphi4 KB (650 words) - 17:50, 13 January 2021
- |package name 1=intel,fcbga_1515 ...Turbo Boost}} frequency of 3.2 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's {{intel|HD Grap4 KB (652 words) - 18:04, 28 August 2018
- |package module 1={{packages/intel/fcbga-1356}} ...Turbo Boost}} frequency of 3.1 GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphi5 KB (799 words) - 17:27, 17 February 2023
- ...e coming from the [[Voltage Regulator Module]] (VRM) is fed to the RVDD, a package metal plane that distributes the highest VID request from all cores. In Zen [[File:amd zen package metal plane.png|350px]]79 KB (12,095 words) - 15:27, 9 June 2023
- ...rediction. 31 entries are usable in single-threaded mode, 15 per thread in dual-threaded mode. At the address of a CALL instruction the address of the foll ...tel's MBA. The L3 cache is not a last level cache shared by all cores in a package as on Intel CPUs, so each CCX corresponds to one QoS domain. L2 QoS monitor57 KB (8,701 words) - 22:11, 9 October 2022
- | package 0 = fcBGA-1296 | package 0 type = fcBGA6 KB (633 words) - 16:25, 13 December 2017
- |package 0=fcBGA-1296 |package 0 type=fcBGA5 KB (584 words) - 18:02, 9 February 2019
- | package 0 = fcBGA-1296 | package 0 type = fcBGA6 KB (639 words) - 12:32, 9 May 2018
- | package 0 = fcBGA-1296 | package 0 type = fcBGA6 KB (642 words) - 16:25, 13 December 2017
- | package 0 = fcBGA-1296 | package 0 type = fcBGA7 KB (847 words) - 20:58, 21 October 2023
- | package 0 = fcBGA-1296 | package 0 type = fcBGA7 KB (837 words) - 23:15, 25 August 2019
- |package module 1={{packages/intel/lga-1151}} ...ncy of 4.2 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's {{intel|HD Graphi5 KB (674 words) - 19:57, 22 October 2019
- |package module 1={{packages/intel/lga-1151}} ...ncy of 3.8 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's {{intel|HD Graphi5 KB (694 words) - 23:04, 15 April 2019
- |package module 1={{packages/intel/lga-1151}} ...ncy of 4.5 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's {{intel|HD Graphi5 KB (699 words) - 11:45, 15 April 2019
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