• c
  ...anguage. It's this precise simplicity and abstraction that allowed various system designers to support C on their architectures. Today, support for the C lan .... UNIX was originally written in assembly language, like most programs and operating systems of the time. Debugging code written in assembly was difficult and s
  5 KB (790 words) - 13:36, 2 October 2017
• mips/coprocessor 0
  ...{{mips|MIPS64}} ISA which provides the facilities needed for an operating system.
  3 KB (384 words) - 10:11, 19 February 2018
• Lua Standard Libraries
  ...nput/out processing, and various other facilities for performing operating system services. The standard libraries functions are implemented directly through
  3 KB (419 words) - 23:30, 1 March 2014
• c/program structure
  ...ay button, or using the Ctrl+F5 shortcut. If you are using a UNIX or Linux system, you should be able to compile the program using the following command: ...ult your operating system's documentation, or an expert familiar with your system's environment, for more detailed information.
  8 KB (1,338 words) - 15:16, 9 March 2016
• intel/quark/x1000
  ...was first announced on October, 2013. The processor has a 400 MHz maximum operating frequency with power options to run at half or at quarter of the maximum fr [[Category:System on a chip]]
  2 KB (240 words) - 03:33, 15 February 2016
• microprocessor
  ...system on a single [[integrated circuit]], or as a few integrated circuits operating as a cohesive unit, designed for the processing digital data. ...D driver]]s, and [[FPGA]]. SoCs are capable of running full-fledged modern operating systems with all their features.
  8 KB (1,149 words) - 00:41, 16 September 2019
• fairchild/pps-25
  The '''PPS-25''' (also '''PPS25'''; '''Programmed Processor System - 25 Digits''') was a [[microprocessor family|family]] of [[4-bit architect ...fic calculations. The system was 25-digit (100-bit) seriel, 4-bit parallel operating at 62.5 µs word time and 2.5 µs bit time. That is, the addition of two wo
  2 KB (291 words) - 23:48, 10 July 2017
• resident set size
  ...set size. The use of RSS is often used in making decisions on whether the system had enough space to swap the process when it entered the [[ready queue]]. ...elves are shown. The exact fields are not always the same across different operating systems, however, on Linux, RSS is the 24th field. The field has ''%ld'' [[
  5 KB (692 words) - 10:20, 3 June 2020
• microprocessors used in spacecrafts
  ! style="width: 25%;" | System !! Processor !! Frequency !! Memory !! Weight ...972, became the first spacecraft to achieve escape velocity from the Solar System. The spacecraft's process were made of individual [[transistor-transistor l
  11 KB (1,334 words) - 18:26, 10 May 2019
• mirc/identifiers/$chan
  | '''hwnd''' || Returns the [[Operating system|operating system's]] actual [[hWnd|window handle]] for the channel.
  4 KB (535 words) - 14:59, 17 February 2024
• mirc/identifiers/$os
  {{mirc title|$os identifier}}'''$os''' returns the name of the operating system you are running
  449 bytes (56 words) - 00:13, 18 February 2024
• vacuum tube computer
  A '''vacuum tube computer''' is a computer system built primarily using [[vacuum tube]]s and [[vacuum tube logic]]. Vacuum tu ...ubes prove to be a significant improvement over electromechanical relays - operating 1000 times faster. However the performance advantage came at the cost of de
  3 KB (347 words) - 03:53, 24 December 2015
• electronic associates/pace 231r
  ...mputer becoming the most widely used analog computer system in the world - operating in various places well into the late 1970s and even early 1980s.
  4 KB (597 words) - 03:48, 23 December 2015
• microcontroller
  ...SoC) which are much more powerful devices, capable of executing modern-day operating systems and applications.
  2 KB (344 words) - 15:51, 21 March 2024
• rockwell international/pps-4-1
  ...]] and [[program memory]] incorporated internally, making it a single-chip system (hence the "/1"). It's full compatible with all the original PPS-4 CPU and ...considerably slower than their {{rockwell|pps-4|multi-chip counterparts}}, operating at only up to half of their frequency (40 KHz-100 KHz).
  2 KB (219 words) - 01:00, 19 May 2016
• intel/atom
  | type = system on chips ...tra-low-voltage]] {{arch|32|32}} and {{arch|64}} [[microprocessor]]s and [[system on chip]]s designed by [[Intel]] since 2008.
  17 KB (2,292 words) - 09:32, 16 July 2019
• amd/athlon
  ...d in 1999, uses {{amd|Slot A}}, has a double data rate [[front side bus]] operating at 100 MHz (having an effective bus speed of 200 MHz). Argon microprocessor ...00 and use {{amd|Slot A}}. They have a double data rate [[front side bus]] operating at 100 MHz (having an effective bus speed of 200 MHz). Pluto microprocessor
  10 KB (1,163 words) - 10:41, 26 February 2019
• intel/atom x3/x3-c3130
  ...3G modem. Manufactured in [[28 nm lithography process|28 nm process]] and operating at 1 GHz, this SoC is aimed at entry-level smart phones. This SoC integrate
  4 KB (424 words) - 16:15, 13 December 2017
• intel/atom x3/x3-c3445
  ...e x3-C3445 is one of Intel's first SoC to integrate a 4G LET 5-mode modem. Operating in 1.2 GHz with a burst frequency of 1.4 GHz, this chip has a scenario desi
  4 KB (467 words) - 16:15, 13 December 2017
• intel/atom x3/x3-c3405
  ...5}} except for its networking capabilities which are limited to WiFi only. Operating in 1.2 GHz with a burst frequency of 1.4 GHz, this chip has a scenario desi
  4 KB (418 words) - 16:15, 13 December 2017
• intel/microarchitectures/bonnell
  ...ly, manufacturers were allowed to use the '''Centrino Atom''' brand if the system consist of a Bonnell-based processor, the chipset, wireless capabilities ([ ...ase in the world, including the ability to run any other [[x86]] operating system unmodified. At the same time it forced the design team to resort to other m
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures
  ...C|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustaine
  3 KB (384 words) - 20:59, 8 February 2022
• intel/microarchitectures/sandy bridge (client)
  ...on versus its {{intel|microarchitectures|predecessors}} resulting a full [[system on a chip]] design. * New {{intel|System Agent}} architecture
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  * [[System Agent]] ** System [[DRAM]]:
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ** System [[DRAM]]: * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual [[FSB]] sp
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ...onnect architecture}} along with {{\\|Gen11}} GPU, and an improved {{intel|System Agent}} with a new display engine and I/O. ...{{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The
  23 KB (3,613 words) - 12:31, 20 June 2021
• x86/umip
  ...a general purpose register. These instructions are intended for operating system use and date back to the Intel {{intel|80286}} microarchitecture. SMSW was ...in turn point to interrupt handler code. CR0 contains flags which control operating modes of the processor. User-mode code was never able to load values into t
  2 KB (338 words) - 01:25, 30 December 2019
• intel/turbo boost technology
  ...bo Boost and have the feature enabled and supported (e.g. most [[operating system|OSs]]). Under various workloads, especially ones that are relatively low in ...bled or enabled. Additionally, Turbo Boosts operates under the [[operating system]]'s control and is engaged automatically when the OS requests the highest p
  7 KB (990 words) - 14:39, 23 July 2022
• intel/80486/486dx2-40
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). * {{intel|System Management Mode}} (SMM)
  2 KB (240 words) - 16:13, 13 December 2017
• intel/80486/486dx2-50
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). * {{intel|System Management Mode}} (SMM)
  3 KB (345 words) - 16:13, 13 December 2017
• intel/80486/486dx2-66
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). * {{intel|System Management Mode}} (SMM)
  4 KB (372 words) - 06:28, 15 February 2024
• intel/80486/486dx4-75
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as th * {{intel|System Management Mode}} (SMM)
  3 KB (354 words) - 16:13, 13 December 2017
• intel/80486/486dx4-100
  ...ip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as th * {{intel|System Management Mode}} (SMM)
  4 KB (414 words) - 16:13, 13 December 2017
• intel/80486/486sx2-50
  ...el|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX * {{intel|System Management Mode}} (SMM)
  2 KB (253 words) - 16:14, 13 December 2017
• intel/80486/486sx2-66
  ...el|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 66 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX * {{intel|System Management Mode}} (SMM)
  2 KB (220 words) - 16:14, 13 December 2017
• amd/am5x86/am486dx5-133w16bhc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (324 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133w16bgc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (358 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133v16bhc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (342 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133v16bgc
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (337 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133adw
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (336 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133adz
  ...is chip as Pentium-75-comparable performance. Due to this processor's high operating temperature rating, it became a favorite among computer enthusiasts who oft * [[has feature::System Management Mode]] (SMM)
  3 KB (372 words) - 16:35, 9 July 2018
• amd/am5x86/amd-x5-133sfz
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (303 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133sdz
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (295 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133ady
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (298 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133sfw
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (289 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133sdw
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (289 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133sdy
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (289 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133sfy
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 4x, operating at 133 MHz with a bus speed of 33 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (289 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-150adw
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 3x, operating at 150 MHz with a bus speed of 50 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (298 words) - 21:32, 10 April 2021
• amd/am5x86/amd-x5-150ady
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 3x, operating at 150 MHz with a bus speed of 50 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (298 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-150adz
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 3x, operating at 150 MHz with a bus speed of 50 MHz. This MPU had all the features offere * [[has feature::System Management Mode]] (SMM)
  3 KB (298 words) - 20:13, 15 March 2021
• amd/am5x86/amd-x5-160
  ...their {{amd|Am5x86}} family. This processor had a clock multiplier of 3x, operating at 150 MHz with a bus speed of 50 MHz. This MPU had all the features offere ...rs). Fake 160 chips were most likely {{\\|AMD-X5-133ADZ}} which had a high operating temperature which made them fairly stable overclocked to 160 MHz anyway.
  4 KB (419 words) - 15:19, 13 December 2017
• intel/iapx
  * {{intel|iRMX}} - Real-time operating system Additionally Intel used a numbering suffix to indicate the type of system configuration dealt with.
  1 KB (168 words) - 05:47, 22 May 2016
• amd/am286zx-lx/ng286lx-12
  ...ed in late 1990. This chip, which incorporated the {{amd|N80C286-12}} core operating at 12 MHz integrated with all the other components typically found on an IB * CPU shutdown mode; System shutdown mode
  3 KB (339 words) - 15:18, 13 December 2017
• amd/am286zx-lx/ng286lx-16
  ...ed in late 1990. This chip, which incorporated the {{amd|N80C286-16}} core operating at 16 MHz integrated with all the other components typically found on an IB * CPU shutdown mode; System shutdown mode
  3 KB (339 words) - 15:18, 13 December 2017
• amd/am286zx-lx/ng286zx-12
  ...ed in late 1990. This chip, which incorporated the {{amd|N80C286-12}} core operating at 12 MHz integrated with all the other components typically found on an IB
  3 KB (309 words) - 15:18, 13 December 2017
• amd/am286zx-lx/ng286zx-16
  ...ed in late 1990. This chip, which incorporated the {{amd|N80C286-16}} core operating at 16 MHz integrated with all the other components typically found on an IB
  3 KB (309 words) - 15:18, 13 December 2017
• 2001
  * March 20: [[Qualcomm]] announces the {{qualcomm|MSM6xxx}} family of system on chips with [[2G]] and [[3G]] support ...me, a prototype CMOS transistor with a 15-nanometer gate length and an 0.8 operating voltage with a switching speed of 300 fs (0.3 ps).
  1 KB (145 words) - 22:48, 27 November 2017
• 1996
  * January 25: [[P-Rating]] system specification were finalized. ...[AMD]], [[IBM]], [[SGS-Thomson]], and [[Cyrix]] announced the [[P-Rating]] system.
  503 bytes (61 words) - 11:57, 28 May 2018
• exponential technology/x704
  ...time - 533 MHz. Comparable chips at the time of Exponential founding were operating at only 50-75 MHz max. By [[1993]] the idea was backed by [[Apple]] and the ...the lay off of thousands employees they will no longer be able to design a system around the X704 chip. This decision had devastating consequences for Expone
  8 KB (1,228 words) - 20:49, 2 June 2019
• p-rating/ibm microelectronics: four companies announce new, simplified method for consumers to measure microprocessor performance in pcs
  ...or revolutions per minute, to indicate how fast the automobile's engine is operating. According to the P-rating developers, "MHz" resembles the RPM measurement, ...en compared with Intel Pentium processors. For example, under the P-rating system announced today, a processor that delivers performance comparable to a 150
  3 KB (423 words) - 17:17, 21 August 2016
• processor performance rating (p-rating) specification
  ...and failed to provide a good measure of real application performance. This system provides a single rating number for a processor (the P-rating) that gives a * To ensure wide acceptance by the processor manufacturers, system vendors, the press, and end users
  11 KB (1,244 words) - 06:26, 8 July 2020
• princeton/piton
  ...64-bit [[network on chip]] (NoC) interconnect made of 3 physical networks operating with a 1 cycle/hop latency. ...national Conference on Architectural Support for Programming Languages and Operating Systems 2016 Mar 25 (pp. 217-232). ACM.
  6 KB (731 words) - 15:41, 5 July 2018
• amd/microarchitectures/zen
  * Cache system ** System DRAM:
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  * System DRAM ...Die shots suggest two execution blocks splitting the PRF and FP ALUs, one operating on the lower 128 bits of a YMM register, executing x87, MMX, SSE, and AVX i
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/xeon e5/e5-2699a v4
  ...s designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.4 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single a ...10 10:49:26-0500|chip_count=2|core_count=44|copies_count=88|vendor=Fujitsu|system=PRIMERGY RX2560 M2, Intel Xeon E5-2699A v4, 2.40GHz|SPECrate2017_fp_base=14
  7 KB (1,005 words) - 17:28, 14 November 2023
• intel/xeon e5/e5-2698 v4
  ...s designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single a ...-0500|chip_count=2|core_count=40|copies_count=80|vendor=Inspur Corporation|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)|SPECrate2017_int_base=143|SPECrate2
  6 KB (644 words) - 16:28, 13 December 2017
• intel/xeon e5/e5-2699 v4
  ...s designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single a ...-10-16 23:43:00-0400|chip_count=2|core_count=44|thread_count=44|vendor=HPE|system=ProLiant ML350 Gen9 (2.20 GHz, Intel Xeon E5-2699 v4)|SPECspeed2017_fp_base
  6 KB (650 words) - 14:28, 28 July 2023
• intel/xeon e5/e5-2650 v4
  ...rver MPU is designed for advanced 2S environments (1U square form factor). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 2.9 GHz for a single a ...-0400|chip_count=2|core_count=24|copies_count=48|vendor=Inspur Corporation|system=Inspur NF5170M4 (Intel Xeon E5-2650 v4)|SPECrate2017_int_base=105|SPECrate2
  5 KB (570 words) - 22:36, 26 March 2023
• intel/xeon e5/e5-2620 v4
  ...rver MPU is designed for standard 2S environments (1U square form factor). Operating at 2.1 GHz with a {{intel|turbo boost}} frequency of 3 GHz for a single act ...-02-28 06:34:33-0500|chip_count=2|core_count=16|copies_count=32|vendor=H3C|system=H3C R4900 G2 (Intel Xeon E5-2620 v4, 2.10 GHz)|SPECrate2017_fp_base=76|SPEC
  5 KB (620 words) - 16:27, 13 December 2017
• intel/xeon e3/e3-1225 v6
  ...400 ECC memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.15 GHz. ...0-22 08:02:53-0400|chip_count=1|core_count=4|copies_count=4|vendor=Fujitsu|system=PRIMERGY TX1330 M3, Intel Xeon E3-1225 v6, 3.3 GHz|SPECrate2017_int_base=21
  4 KB (667 words) - 16:26, 13 December 2017
• amd/athlon mp
  ...760MP}} supports one- and two-way setups and Double Data Rate (DDR) memory operating at 133 MHz. At the time, AMD's vice president for their servers group state ...] and a 128 KiB [[L1$]]. As with all [[Socket A]] processors ({{decc|EV6}} system bus), Athlon MP operate on a 133 MHz FSB DDR (double data rate) yielding an
  11 KB (1,571 words) - 18:57, 17 November 2016
• amd/athlon mp/ahx1200ans3b
  ...market. This particular model, which operated at 1.2 GHz, had a lower FSB operating at 100 MHz (for an effective transfer rate of 200 MT/s) and operated at hig ...rations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors.pdf|System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Facto
  4 KB (538 words) - 15:20, 13 December 2017
• mediatek/helio
  | type = System on chips '''Helio''' is a family of {{arch|64}} multi-core [[ARM]] [[system on chip]]s developed by [[MediaTek]] and launched in [[2015]]. Helio was Me
  7 KB (902 words) - 16:33, 12 January 2023
• mediatek/helio/mt6795
  ...3-1866 memory. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) ca
  5 KB (669 words) - 14:35, 5 August 2020
• mediatek/helio/mt6795m
  ...l LPDDR3-1866. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 550 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) cat
  6 KB (647 words) - 09:57, 12 January 2018
• mediatek/helio/mt6795t
  ...l LPDDR3-1866. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) cat
  6 KB (670 words) - 09:36, 22 August 2018
• mediatek/helio/mt6797
  ...3-1866 memory. This SoC also incorporates a {{armh|Mali-T800 MP4}} [[IGP]] operating at 780 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) cat
  6 KB (713 words) - 21:16, 2 May 2021
• mediatek/helio/mt6797m
  ...3-1866 memory. This SoC also incorporates a {{armh|Mali-T800 MP4}} [[IGP]] operating at 780 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) cat
  6 KB (617 words) - 02:35, 14 December 2019
• mediatek/helio/mt6797t
  ...X-3200 memory. This SoC also incorporates a {{armh|Mali-T880 MP4}} [[IGP]] operating at 850 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) cat
  5 KB (581 words) - 14:25, 12 September 2019
• mediatek/helio/mt6797d
  ...3-1600 memory. This SoC also incorporates a {{armh|Mali-T800 MP4}} [[IGP]] operating at 780 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) cat
  5 KB (574 words) - 04:36, 23 June 2019
• mediatek/helio/mt6797x
  ...3-1600 memory. This SoC also incorporates a {{armh|Mali-T800 MP4}} [[IGP]] operating at 780 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) cat
  5 KB (600 words) - 08:55, 12 October 2023
• mediatek/helio/mt6799
  ...emory. This SoC also incorporates a {{imgtec|PowerVR GT7400 Plus}} [[IGP]] operating at 800 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) cat
  4 KB (549 words) - 16:22, 29 December 2018
• mediatek/helio/mt6755
  ...PDDR3-1866 memory. This chip incorporates the {{imgtec|Mali-T860}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) ca ...ch linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 2 GHz and 1.2 GHz respectively.
  5 KB (696 words) - 17:41, 15 August 2020
• mediatek/helio/mt6755m
  ...PDDR3-1866 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 650 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) ca ...ch linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 1.8 GHz and 1.2 GHz respectively.
  5 KB (614 words) - 09:40, 12 February 2020
• mediatek/helio/mt6755t
  ...PDDR3-1866 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 800 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) ca ...ch linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 2.2 GHz and 1.2 GHz respectively.
  4 KB (552 words) - 23:18, 3 November 2019
• mediatek/helio/mt6757
  ...DDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) ca
  4 KB (473 words) - 04:40, 23 June 2019
• mediatek/helio/mt6757cd
  ...DDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 1 GHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) categ
  4 KB (564 words) - 06:22, 30 March 2021
• cavium/octeon
  | type = System on chips ..., and [[RegEx]]. Additionally, these models support a faster [[PCI-X]] bus operating up to 100 MHz, gigabit Ethernet ([[GMII]]), and up to DDR2-667 ECC memory.
  11 KB (1,489 words) - 09:25, 30 December 2020
• acpi/c-states
  ...her components, there are multiple C-states depending on which part of the system is talked about. In practice there are usually 3 general C-states: * '''OS C-state''' - a set of logical idle states provided by the [[operating system]] to the [[application software]]. Those states are logical c-state and may
  4 KB (635 words) - 08:08, 11 November 2018
• qualcomm/microarchitectures/falkor
  ...me of the core architecture ressmbles Qualcomm's mobile cores, the overall system architecture is considerably different to anything Qualcomm has previously ** 1 V nominal operating voltage
  6 KB (822 words) - 13:01, 19 May 2021
• acorn/microarchitectures/arm1
  ...corn's [[BBC Micro]] microcomputers. ARM1 was distributed as an evaluation system and was never commercialized. ...ginal [[IBM]] {{ibm|PC AT}} or that of the [[Motorola]] {{motorola|68020}} operating at 16.67 MHz.
  12 KB (1,886 words) - 12:56, 14 January 2021
• arm/history
  ...torola {{motorola|68000}}, a much more powerful {{arch|16}} microprocessor operating at 5 MHz. The Lisa included many other cutting edge features such as a wind [[File:Acorn-ARM-Evaluation-System.jpg|left|thumb|[[ARM1]] Evaluation System board. The microprocessor in the center is the {{vti|VC2588}}.]]
  6 KB (834 words) - 01:12, 29 January 2019
• samsung/exynos/3110
  ...h}} core operating at 1 GHz along with a {{imgtec|PowerVR SGX540}} [[IGP]] operating at 200 MHz. This SoC supports up to LPDDR2-400 dual-channel memory.
  4 KB (533 words) - 21:28, 27 March 2018
• xiaomi/surge/s1
  ...T860}} MP4 [[IGP]]. The S1 is Xiaomi's first generation in-house developed system-on-chip.
  4 KB (386 words) - 04:42, 7 April 2022
• xiaomi/surge/s2
  ...ing at up to 2.7 GHz with another four low-power {{armh|Cortex-A53}} cores operating at 2 GHz. This processor is fabricated on TSMC's [[10 nm process]] and inco
  3 KB (309 words) - 15:24, 5 September 2018
• loongson/godson 2/2h
  ...son-2H also incorporates a low-power [[Vivante]] {{vivante|GC800}} [[IGP]] operating at 400 MHz. This chip has integrated [[HyperTransport]] 1.03 operating at 200, 400, or 800 MHz.
  5 KB (591 words) - 16:31, 13 December 2017
• intel/atom/z605
  ...onally, the Z605 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz. ...h is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 200 MHz for a 800 MT/s effective rate. This model uses a [[GTL|AGTL+]] sign
  6 KB (775 words) - 16:14, 13 December 2017
• intel/atom/z600
  ...onally, the Z600 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 200 MHz. ...h is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 100 MHz for a 400 MT/s effective rate. This model uses CMOS signaling for b
  6 KB (782 words) - 16:14, 13 December 2017
• intel/atom/z650
  ...onally, the Z650 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz. ...h is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 200 MHz for a 800 MT/s effective rate. This model uses a [[GTL|AGTL+]] sign
  6 KB (774 words) - 16:15, 13 December 2017

View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)