Semiconductor & Computer Engineering
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- | microarch 6 = Broadwell | proc = 45 nm43 KB (5,739 words) - 21:30, 22 April 2024
- | microarch 6 = Westmere | proc = 350 nm13 KB (1,417 words) - 12:37, 22 December 2018
- |process=5 nm |process 2=6 nm4 KB (693 words) - 01:48, 2 April 2023
- |process=5 nm |process 2=6 nm4 KB (666 words) - 01:48, 2 April 2023
- [[File:intel mask.jpg|right|thumb|Modern Intel 6" [[14 nm]]/[[10 nm]] test reticle.]]3 KB (533 words) - 17:17, 29 January 2024
- | process = 22 nm |l3 cache=6 MiB4 KB (404 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (401 words) - 14:24, 12 February 2019
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (400 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:22, 13 December 2017
- |process=22 nm |l3 cache=6 MiB3 KB (386 words) - 09:14, 26 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (401 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (397 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (398 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB4 KB (406 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (396 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (391 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:20, 13 December 2017
- |core family=6 |process=14 nm4 KB (640 words) - 02:21, 16 January 2019
- |core family=6 |process=14 nm4 KB (650 words) - 02:21, 16 January 2019
- | process = 14 nm |l3 cache=6 MiB4 KB (407 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (401 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (395 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (424 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (405 words) - 16:22, 13 December 2017
- |process=14 nm |l3 cache=6 MiB4 KB (460 words) - 15:03, 24 March 2019
- |core family=6 |process=14 nm4 KB (631 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (649 words) - 16:20, 13 December 2017
- | proc = 45 nm | proc 2 = 32 nm17 KB (2,292 words) - 09:32, 16 July 2019
- | proc = 800 nm | proc 2 = 600 nm10 KB (1,057 words) - 19:30, 1 November 2021
- | microarch 6 = Excavator | proc = 32 nm6 KB (700 words) - 15:43, 1 December 2019
- ...lithography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patter10 KB (1,090 words) - 19:14, 8 July 2021
- ...e 14 nm node was introduced in 2014/2015 and has been replaced by the [[10 nm process]]. | process 1 lith = 193 nm17 KB (2,243 words) - 19:32, 25 May 2023
- | process = 14 nm |l1d desc=6-way set associative4 KB (462 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative4 KB (472 words) - 16:15, 13 December 2017
- |process=14 nm |l1d desc=6-way set associative4 KB (475 words) - 17:42, 27 March 2018
- | process = 14 nm |l1d desc=6-way set associative5 KB (573 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative5 KB (572 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative6 KB (744 words) - 18:35, 14 January 2019
- |process=14 nm |l1d desc=6-way set associative5 KB (736 words) - 03:44, 19 August 2023
- | process = 14 nm |l1d desc=6-way set associative5 KB (558 words) - 16:15, 13 December 2017
- ...lithography process|40 nm process]] (HN) / [[32 nm lithography process|32 nm process]] (FN) in 2010. ...on, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-5 KB (602 words) - 05:51, 20 July 2018
- |process=45 nm |extension 6=SSSE338 KB (5,468 words) - 20:29, 23 May 2019
- | process = 32 nm | extension 6 = SSSE37 KB (872 words) - 19:42, 30 November 2017
- | process = 22 nm | extension 6 = SSSE39 KB (1,160 words) - 09:35, 25 September 2019
- | process = 14 nm | extension 6 = SSSE35 KB (568 words) - 19:40, 30 November 2017
- |process=14 nm |extension 6=SSSE37 KB (956 words) - 23:05, 23 March 2020
- | microarch 6 = Haswell | proc = 45 nm20 KB (2,661 words) - 00:45, 11 October 2017
- | microarch 6 = Westmere | proc = 350 nm25 KB (3,201 words) - 03:13, 22 September 2018
- |process=14 nm |tdp=6.5 W4 KB (529 words) - 17:41, 27 March 2018
- |process=14 nm |tdp=6 W5 KB (701 words) - 17:40, 27 March 2018
- |process=14 nm |tdp=6 W4 KB (540 words) - 17:40, 27 March 2018
- |process=14 nm ...d by Intel and introduced in early 2015. The N3000 is manufactured in [[14 nm process]] based on the {{intel|Airmont}} microarchitecture. This chip opera4 KB (544 words) - 17:43, 27 March 2018
- |process=14 nm |tdp=6 W4 KB (580 words) - 09:40, 8 July 2022
- |process=14 nm |tdp=6 W5 KB (724 words) - 06:10, 2 December 2018
- |process=14 nm ...d by Intel and introduced in early 2016. The N3010 is manufactured in [[14 nm process]] based on the {{intel|Airmont}} microarchitecture. This chip opera4 KB (539 words) - 17:39, 27 March 2018
- |process=14 nm ...based on the {{intel|Airmont}} microarchitecture. This chip operates at 1.6 GHz with turbo mode of up to 2.24 GHz. This SoC incorporates the {{intel|HD4 KB (535 words) - 17:39, 27 March 2018
- |process=14 nm |tdp=6 W5 KB (722 words) - 01:50, 24 November 2018
- |process=14 nm |tdp=6 W4 KB (533 words) - 17:41, 27 March 2018
- |process=14 nm |tdp=6 W4 KB (539 words) - 17:39, 27 March 2018
- |core family=6 |core model=64 KB (593 words) - 02:17, 1 April 2019
- |core family=6 |core model=64 KB (593 words) - 02:18, 1 April 2019
- |core family=6 |core model=64 KB (582 words) - 02:21, 1 April 2019
- |core family=6 |core model=64 KB (596 words) - 02:18, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (593 words) - 02:17, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (596 words) - 02:17, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 09:36, 14 May 2021
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:18, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:16, 1 April 2019
- |core family=6 |core model=64 KB (595 words) - 02:17, 1 April 2019
- |process=14 nm |cores 3=614 KB (1,891 words) - 14:37, 6 January 2022
- |process=22 nm |cores 3=627 KB (3,750 words) - 06:57, 18 November 2023
- ...hy process|20 nm process]] (HN) in 2014 and [[16 nm lithography process|16 nm process]] (FN) in late 2015. The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the7 KB (891 words) - 09:52, 25 November 2020
- | microarch 6 = Broadwell | proc = 45 nm4 KB (572 words) - 16:03, 1 June 2017
- | core family = 6 | process = 45 nm4 KB (522 words) - 20:46, 4 October 2018
- | core family = 6 | process = 45 nm4 KB (537 words) - 15:01, 13 December 2019
- | process = 22 nm ...ge''' ('''IVB''') was [[Intel]]'s [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a5 KB (689 words) - 13:44, 2 May 2020
- |process=32 nm ...formerly '''Gesher''', is [[Intel]]'s successor to {{\\|Westmere}}, a [[32 nm process]] [[microarchitecture]] for mainstream workstations, desktops, and84 KB (13,075 words) - 00:54, 29 December 2020
- | process = 32 nm '''Westmere''' ('''WSM''') was the [[microarchitecture]] for [[Intel]]'s [[32 nm process]] for desktops and servers. Westmere was introduced in 2010 as a [[10 KB (1,258 words) - 21:07, 9 March 2018
- | process = 45 nm '''Penryn''' was the [[microarchitecture]] for [[Intel]]'s [[45 nm process]] for desktops and servers as a successor to {{\\|Core}}. Penryn wa1 KB (133 words) - 21:08, 9 March 2018
- |process=14 nm |extension 6=SSSE379 KB (11,922 words) - 06:46, 11 November 2022
- |process=14 nm |extension 6=SSSE338 KB (5,431 words) - 10:41, 8 April 2024
- |process=10 nm |extension 6=SSSE37 KB (887 words) - 12:53, 5 August 2019
- |process=10 nm |extension 6=SSSE323 KB (3,613 words) - 12:31, 20 June 2021
- |process=10 nm |cores 3=63 KB (406 words) - 10:46, 19 July 2023
- | bus rate = 6.4 GT/s | process = 32 nm4 KB (419 words) - 16:24, 13 December 2017
- | bus rate = 6.4 GT/s | process = 32 nm4 KB (414 words) - 16:24, 13 December 2017
- ...lithography process|55 nm process]] (HN) / [[45 nm lithography process|45 nm process]] (FN) in 2007. ...nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ4 KB (407 words) - 05:55, 20 July 2018
- | last shipment = March 6, 2015 | platform = 6 Series Chipset5 KB (517 words) - 23:32, 22 September 2019
- | last shipment = March 6, 2015 | platform = 6 Series Chipset4 KB (456 words) - 16:24, 13 December 2017
- |process=22 nm |core count=64 KB (492 words) - 23:23, 12 March 2019
- |core family=6 |process=32 nm5 KB (710 words) - 16:24, 13 December 2017
