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Ice Lake (client) µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	2019
Process	10 nm
Instructions
ISA	x86-64
Cache
L1I Cache	32 KiB/core 8-way set associative
L1D Cache	48 KiB/core 12-way set associative
L2 Cache	512 KiB/512 KiB 12-way set associative
L3 Cache	2 MiB/core 16-way set associative
Cores
Core Names	Ice Lake Y, Ice Lake U
Succession
Cannon Lake Tiger Lake
Contemporary
Ice Lake (server)

Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Codenames

Core	Abbrev	Description	Graphics	Target
Ice Lake Y	ICL-Y	Extremely low power		2-in-1s detachable, tablets, and computer sticks
Ice Lake U	ICL-U	Ultra-low Power		Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Ice Lake H	ICL-H	High-performance Graphics		Ultimate mobile performance, mobile workstations
Ice Lake S?	ICL-S	Performance-optimized lifestyle		Desktop performance to value, AiOs, and minis

Process Technology

See also: Cannon Lake § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler	Arch-Specific	Arch-Favorable
ICC	-march=icelake	-mtune=icelake
GCC	-march=icelake	-mtune=icelake
LLVM	-march=icelake	-mtune=icelake
Visual Studio	/?	/tune:?

CPUID

Core	Extended Family	Family	Extended Model	Model
U, Y	0	0x6	0x7	0xE
	Family 6 Model 126
?	0	0x6	?	?
	Family 6 Model ?

Architecture

Ice Lake comprises of Sunny Cove cores on the ring interconnect architecture along with Gen11 GPU, and an improved System Agent with a new display engine and I/O.

Key changes from Cannon Lake

• Enhanced "10nm+" (from "10nm", 2nd gen)
• Sunny Cove core (from Palm Cove)
  • See Sunny Cove for microarchitectural details and changes
• Gen10 → Gen11 graphics
• Gen11 GPUs
  • UHD Graphics 7xx (GT1) → UHD Graphics 9xx (GT2) (32 Execution Units, 1.3x EUs from Cannon Lake)
  • UHD Graphics 7xx (GT2) → Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 1.2-1.6x EUs from Cannon Lake)
• Display
  • DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)
  • HDMI 2.0 (from HDMI 1.4)
• IPU
  • 4th Gen IPU (from 3rd Gen in Skylake)
• I/O
  • Thunderbolt 3 over Type-C

This list is incomplete; you can help by expanding it.

New instructions

Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.

Block Diagram

Entire SoC Overview

Individual Core

See Sunny Cove § Block Diagram.

Gen11 Graphics

See Gen11 Graphics § Block Diagram.

Overview

This section is empty; you can help add the missing info by editing this page.

Core

This section is empty; you can help add the missing info by editing this page.

IPU =

This section is empty; you can help add the missing info by editing this page.

Die

System Agent

• System Agent
  • 4th Gen IPU
  • Gen11 Display
  • Thunderbolt 3 over Type-C
  • PCIe

Core

Core group

Integrated graphics

SoC

• 10 nm process
• 4 Sunny Cove big cores
• 64-EU Gen11 GPU
• 4th Gen IPU

All Ice Lake Chips

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

	List of Ice Lake-based Processors
	Main processor										Turbo Boost				Memory	GPU			Features
Model	Launched	Price	Family	Platform	Core	Cores	Threads	L3$	TDP	Base	1 Core	2 Cores	4 Cores	6 Cores	Max Memory	Name	Base	Burst	TBT	HT
Count: 0

Bibliography

• Intel 2018 Architecture Day.
• Intel. personal communication. 2019.