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Change Microarchitecture Infobox Values: intel/microarchitectures/ice lake (client)

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General
Arch TypeThe type of microarchitecture being described.
NameExact name of the microarchitecture
Designer




The name of the designer company
Manufacturer








The name of the manufacturer/foundry
IntroductionWhen the arch was introduced
Phase-OutWhen the arch was replaced.
Process







The technology node used.
Cores Configuration

, , ,
, , ,
, , ,
, , ,

The core configuration used
Pipeline
Type






The pipeline architecture utilized
OoOEIs it out of order? Yes/No
SpeculativeDoes it perform Speculative execution? Yes/No
RenamingDoes it utilize register renaming? Yes/No
Stages# of stages ONLY if fixed number (if min/max use below)
Strages (min-max)

Min:
Max:

Min-Max stages
Decode (ways)Decoders in parallel
Instructions
ISA




The ISA(s) being implemented
Feature




Various features implemented. This is seldom used.
Extension


















































Various extensions implemented. (a ton of x86...)
Cache
L1I$

L1I:
L1I Per:
L1I Desc:

L1I cache info
L1D$

L1D:
L1D Per:
L1D Desc:

L1D cache info
L1$ (Unified)

L1:
L1 Per:
L1 Desc:

Unified L1 cache info
L2$

L2:
L2 Per:
L2 Desc:

L2 cache info
L3$

L3:
L3 Per:
L3 Desc:

L3 cache info
L4$

L4:
L4 Per:
L4 Desc:

L4 cache info
Side$

Side$:
Side$ Per:
Side$ Desc:

Side cache info
Cores
Core Names









Codename for the core/model series
Succession
Predecessor

Pred:
Pred Link:
Pred2:
Pred2 Link:
Pred3:
Pred3 Link:
Pred4:
Pred4 Link:
Pred5:
Pred5 Link:

Predecessor architectures
Successor

Succ:
Succ Link:
Succ2:
Succ2 Link:
Succ3:
Succ3 Link:
Succ4:
Succ4 Link:
Succ5:
Succ5 Link:

Successor architectures
Contemporary

Cont:
Cont Link:
Cont2:
Cont2 Link:
Cont3:
Cont3 Link:
Cont4:
Cont4 Link:
Cont5:
Cont5 Link:

Contemporary architectures

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