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• mos technology
  *{{mos|6530}} ROM/RAM I/O Timer (RRIOT)
  2 KB (269 words) - 18:40, 31 August 2021
• acorn/microarchitectures/arm1
  ...number of separate units is because the ARM1 makes use of [[microcode]] [[ROM]]s ([[PLA]]). Each instruction is decoded into up to four [[µOP]] signal-w
  12 KB (1,886 words) - 12:56, 14 January 2021
• dec/microarchitectures/alpha 21064
  * Directly serial ROM interface
  4 KB (527 words) - 02:09, 4 August 2017
• acorn/microarchitectures/arm2
  ...number of separate units is because the ARM2 makes use of [[microcode]] [[ROM]]s ([[PLA]]). Each instruction is decoded into up to four [[µOP]] signal-w
  14 KB (2,093 words) - 04:42, 10 July 2018
• renesas/r-car/h2
  * Flash ROM and SRAM, Data bus width: 8 or 16 bits
  3 KB (420 words) - 16:32, 13 December 2017
• renesas/r-car/m2
  * Flash ROM and SRAM, Data bus width: 8 or 16 bits
  3 KB (409 words) - 16:32, 13 December 2017
• renesas/r-car/e2
  * Flash ROM and SRAM, Data bus width: 8 or 16 bits
  3 KB (409 words) - 16:32, 13 December 2017
• renesas/r-car/v2h
  * Flash ROM and SRAM Data bus width: 8/16 bit
  2 KB (346 words) - 16:32, 13 December 2017
• ti/tms1000/tms1099
  The TMS1099JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 64x4 bits of RAM, 8 bits o This ROM-less version addresses 1024 x 8 bits on an external memory (EPROM).
  824 bytes (121 words) - 14:56, 13 December 2017
• ti/tms1000/tms1098
  The TMS1098JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 128x4 bits of RAM, 8 bits This ROM-less version addresses 2048 x 8 bits on an external memory (EPROM).
  900 bytes (128 words) - 14:56, 13 December 2017
• intel/documents
  ...', a complete offerings of their products including [[microprocessors]], [[ROM]]s, [[RAM]]s, [[memory]] peripherals, and various other [[ICs]].
  4 KB (448 words) - 15:02, 3 October 2019
• amd/packages/socket tr4
  |PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}}
  86 KB (17,313 words) - 02:48, 13 March 2023
• amd/packages/socket sp3
  |PSP_ROM_CS_L<br/>SPI_TPM_CS_L||O-IO18-S||SPI Chip Select for {{abbr|PSP}} ROM or {{abbr|TPM}} |LPC||ROM,||1=SPI ROM (default)
  110 KB (21,122 words) - 02:46, 13 March 2023
• intel/microarchitectures/sunny cove
  ...ur µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode seq
  34 KB (5,187 words) - 06:27, 17 February 2023
• centaur/microarchitectures/cha
  *** Instruction ROM ...simultaneously controls all the compute slices and memory. The instruction ROM is used for executing validation code as well as commonly-used functions. T
  24 KB (3,792 words) - 04:37, 30 September 2022
• amd/List of AMD publications
  |24406||||AMD Mobile Thermal Kit Documentation and Software CD–ROM||||Family 6 {{amd publ|an|key=AMD-Au1000-BootROM|rev=1.2|title=Mapping a Boot ROM on Alchemy™ Au1000™ Processor from AMD|url=https://web.archive.org/web/
  181 KB (24,894 words) - 16:24, 12 June 2024
• eta compute/ecm353x/ecm3532
  * 8 KiB ROM
  3 KB (460 words) - 02:24, 12 February 2020
• amd/packages/fp6
  |SPI_CS(1-3)_L||Chip Select for SPI ROM or other devices |SPI_ROM_REQ||SPI ROM Request
  20 KB (3,273 words) - 17:47, 10 May 2023
• alchemy/au1200-333mgc
  ...bsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode,
  6 KB (862 words) - 01:16, 19 March 2022
• alchemy/au1000-266mcc
  ...r|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals su
  4 KB (607 words) - 00:41, 16 March 2022

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