• amd/packages/socket am4
  !Signal!!Description |MA0/MA1/MB0/MB1_CKE[1:0]||DRAM Channel A/B DIMM 0/1 Clock Enable
  30 KB (6,098 words) - 01:58, 12 January 2024
• acorn/microarchitectures/arm1
  [[File:two-phase clock.svg|right|300px]] ...d for [[level-triggered]] transfer instead of [[edge-triggering]]. The two clock phases are not generated on-die but come from an external [[oscillator]]. A
  12 KB (1,886 words) - 12:56, 14 January 2021
• clock domain
  ...nals within a specific clock domain only change in response to their clock signal event.
  263 bytes (42 words) - 05:09, 14 April 2017
• acorn/microarchitectures/arm2
  [[File:two-phase clock.svg|right|300px]] ...d for [[level-triggered]] transfer instead of [[edge-triggering]]. The two clock phases are not generated on-die but come from an external [[oscillator]]. A
  14 KB (2,093 words) - 04:42, 10 July 2018
• acorn/microarchitectures/arm3
  ** Integrated clock generator === Clock Generator ===
  7 KB (1,035 words) - 06:24, 21 November 2023
• ibm/microarchitectures/z14
  * Higher clock frequency (5.2 GHz from 5 GHz; 4% increase) ...s in a number of slightly different flavors. In order to reach the highest clock speed of 5.2 GHz, the water cooled system is required, otherwise the air co
  8 KB (1,204 words) - 14:02, 23 September 2019
• intel/microarchitectures/skylake (server)
  ** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 M ...lking more performance by increasing the instructions per cycle as well as clock frequency.
  52 KB (7,651 words) - 00:59, 6 July 2022
• microsoft/scorpio engine
  ! Signal !! Description | (A0-F0/A1-F1)_CKE0 || DRAM Clock Enable for Address/Command Bus
  15 KB (2,390 words) - 02:54, 17 May 2023
• pezy/pezy-scx
  | clock min = 733 MHz | clock max = 1,600 MHz
  6 KB (838 words) - 09:33, 9 May 2019
• intel/microarchitectures/polaris
  * ≥ 5 GHz clock ...s which is used to forward the [[packets]] between the tiles, allowing for clock-phase-insensitive tile-to-tile communication and synchronous operations wit
  16 KB (2,552 words) - 23:22, 17 May 2019
• amd/packages/socket tr4
  ...ity Fabric clock}} so for instance a 1.33 GHz FCLK coupled to the bus clock of DDR4-2666 SDRAM gives a raw data rate of 5.33 GT/s per lane or 21.33&nbs ...s. TR4 packages are not merely EPYC processors with two disabled dies, the signal routing is different. Only the four memory channels pinned out closest to t
  86 KB (17,313 words) - 02:48, 13 March 2023
• amd/packages/socket sp3
  Naffziger2020--> The SerDes run at {{abbr|FCLK|Infinity Fabric clock}} so for instance a 1.33 GHz FCLK coupled to the bus clock of
  110 KB (21,122 words) - 02:46, 13 March 2023
• qualcomm/snapdragon 800/8cx
  |clock multiplier=28x ** Qualcomm Spectra 390 image signal processor
  5 KB (597 words) - 20:19, 16 January 2022
• qualcomm/snapdragon 800/855
  == Clock domains == ...ores from the prior quad-core Gold clock domains has been moved to its own clock domain. Qualcomm refers to that core as a 'Prime' core. The Prime core util
  9 KB (1,235 words) - 12:57, 16 December 2023
• samsung/exynos/9611
  ...well as [[802.11ac]], [[Bluetooth]] 5.0, and a 24 [[megapixel|MP]] [[image signal processor|ISP]]. ...e {{\\|9610|Exynos 9610}} featuring [[little cores]] with a 100 MHz higher clock frequency.
  4 KB (500 words) - 09:23, 3 October 2022
• qualcomm/snapdragon 800/865
  |clock multiplier=28 ** Qualcomm Spectra 480 image signal processor
  7 KB (1,043 words) - 09:30, 23 December 2022
• amd/List of AMD publications
  ...Clock Control (Am486, Am5x86, K5) (August 1995).pdf|Phase Lock Loop (PLL) Clock Control]]||1995-08||Am486, Am5x86, K5 ...[[:File:Clock Gating Recommendations (Am486, Am5x86, K5) (August 1995).pdf|Clock Gating Recommendations]]||1995-08||
  181 KB (24,861 words) - 16:02, 17 April 2022
• amd/packages/socket am2
  !Signal!!Description |CLKIN_H/L||200 MHz Differential PLL Reference Clock
  7 KB (1,029 words) - 18:40, 22 February 2020
• amd/packages/socket am2+
  !Signal!!Description |CLKIN_H/L||200 MHz Differential PLL Reference Clock
  8 KB (1,212 words) - 19:01, 22 February 2020
• cea-leti/microarchitectures/tsarlet
  ...1.25 GHz with the lowest latency of 7.2 ns between source and destination clock domains. For the L2 to L3 tiles a 2-channel 2D-mesh interconnect is utilize ...CVRs make up around 30% of the die area. Each unit is managed by a central clock-frequency and feedback controller with a sub-10ns step response, enabling t
  12 KB (1,895 words) - 10:17, 27 March 2020

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)