Revision as of 23:22, 12 May 2019

Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Codenames

Process Technology

See also: Cannon Lake § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

CPUID

Architecture

Ice Lake comprises of Sunny Cove cores on the ring interconnect architecture along with Gen11 GPU, and an improved System Agent with a new display engine and I/O.

Key changes from Cannon Lake

• Enhanced "10nm+" (from "10nm", 2nd gen)
• Sunny Cove core (from Palm Cove)
  • See Sunny Cove for microarchitectural details and changes
• Gen10 → Gen11 graphics
• Gen11 GPUs
  • UHD Graphics 7xx (GT1) → UHD Graphics 9xx (GT2) (32 Execution Units, 1.3x EUs from Cannon Lake)
  • UHD Graphics 7xx (GT2) → Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 1.2-1.6x EUs from Cannon Lake)
• Display
  • DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)
  • HDMI 2.0 (from HDMI 1.4)
• IPU
  • 4th Gen IPU (from 3rd Gen in Skylake)
• I/O
  • Thunderbolt 3 over Type-C

This list is incomplete; you can help by expanding it.

New instructions

Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.

Block Diagram

Entire SoC Overview

Individual Core

See Sunny Cove § Block Diagram.

Gen11 Graphics

See Gen11 Graphics § Block Diagram.

Overview

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Core

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IPU

Ice Lake incorporates 4th generation image processing unit (IPU). The IPU was first introduced with Skylake mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements.

Die

System Agent

• System Agent
  • 4th Gen IPU
  • Gen11 Display
  • Thunderbolt 3 over Type-C
  • PCIe

Core

Core group

Integrated graphics

SoC

• 10 nm process
• 4 Sunny Cove big cores
• 64-EU Gen11 GPU
• 4th Gen IPU

All Ice Lake Chips

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Bibliography

• Intel 2018 Architecture Day.
• Intel. personal communication. 2019.