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Difference between revisions of "intel/microarchitectures/cannon lake"
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{{intel title|Cannonlake|arch}}
+
{{intel title|Cannon Lake|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
| name             = Cannonlake
+
|atype=CPU
−
| manufacturer     = Intel
+
|name=Cannon Lake
−
| introduction     = 2018-2019
+
|designer=Intel
−
| phase-out        =  
+
|manufacturer=Intel
−
| process         = 10 nm
+
|introduction=May 15, 2018
 +
|process=10 nm
 +
|cores=2
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages min=14
 +
|stages max=19
 +
|decode=5-way?
 +
|isa=x86-64
 +
|extension=MOVBE
 +
|extension 2=MMX
 +
|extension 3=SSE
 +
|extension 4=SSE2
 +
|extension 5=SSE3
 +
|extension 6=SSSE3
 +
|extension 7=SSE4.1
 +
|extension 8=SSE4.2
 +
|extension 9=POPCNT
 +
|extension 10=AVX
 +
|extension 11=AVX2
 +
|extension 12=AES
 +
|extension 13=PCLMUL
 +
|extension 14=FSGSBASE
 +
|extension 15=RDRND
 +
|extension 16=FMA3
 +
|extension 17=F16C
 +
|extension 18=BMI
 +
|extension 19=BMI2
 +
|extension 20=VT-x
 +
|extension 21=VT-d
 +
|extension 22=TXT
 +
|extension 23=TSX
 +
|extension 24=RDSEED
 +
|extension 25=ADCX
 +
|extension 26=PREFETCHW
 +
|extension 27=CLFLUSHOPT
 +
|extension 28=XSAVE
 +
|extension 29=SGX
 +
|extension 30=MPX
 +
|extension 31=AVX-512
 +
|extension 32=AVX-512F
 +
|extension 33=AVX-512CD
 +
|extension 34=AVX-512BW
 +
|extension 35=AVX-512DQ
 +
|extension 36=AVX-512VL
 +
|extension 37=AVX-512IFMA
 +
|extension 38=AVX-512VBMI
 +
|extension 39=SHA
 +
|extension 40=UMIP
 +
|l1i=32 KiB
 +
|l1i per=core
 +
|l1i desc=8-way set associative
 +
|l1d=32 KiB
 +
|l1d per=core
 +
|l1d desc=8-way set associative
 +
|l2=256 KiB
 +
|l2 per=core
 +
|l2 desc=4-way set associative
 +
|l3=2 MiB
 +
|l3 per=core
 +
|l3 desc=Up to 16-way set associative
 +
|core name 2=Cannon Lake Y
 +
|predecessor=Kaby Lake
 +
|predecessor link=intel/microarchitectures/kaby lake
 +
|successor=Ice Lake
 +
|successor link=intel/microarchitectures/ice lake (client)
 +
|contemporary=Coffee Lake
 +
|contemporary link=intel/microarchitectures/coffee lake
 +
|core names=Yes
 +
|succession=Yes
 +
}}
 +
'''Cannon Lake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannon Lake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the second half of [[2018]]. Cannon Lake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
 +
 
 +
For mobile, Cannon Lake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors.
 +
 
 +
== Codenames ==
 +
{| class="wikitable"
 +
|-
 +
! Core !! Abbrev !! Description !! Graphics !! Target
 +
|-
 +
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 +
|}
 +
 
 +
== Release Dates ==
 +
Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.
 +
 
 +
== Process Technology ==
 +
Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell.
 +
 
 +
[[Scaling]]:
 +
 
 +
{| class="wikitable"
 +
|-
 +
! !! Broadwell !! Cannon<br>Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
 +
|-
 +
| || [[14 nm]] || [[10 nm]] ||
 +
|-
 +
| Fin Pitch || &nbsp;42 nm || &nbsp;34 nm || 0.81x
 +
|-
 +
| Fin Width​ || &nbsp;&nbsp;8 nm || &nbsp;&nbsp;7 nm || 0.88x
 +
|-
 +
| Fin Height​ || &nbsp;42 nm || &nbsp;53 nm || 1.24x
 +
|-
 +
| Gate Pitch || &nbsp;70 nm || &nbsp;54 nm || 0.77x
 +
|-
 +
| Interconnect Pitch || &nbsp;52 nm || &nbsp;36 nm || 0.69x
 +
|-
 +
| Cell Height || 399 nm || 272 nm || 0.68x
 +
|}
 +
 
 +
== Compiler support ==
 +
Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[ICC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
 +
|-
 +
| [[GCC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
 +
|-
 +
| [[LLVM]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
 +
|-
 +
| [[Visual Studio]] || <code>?</code> || <code>?</code>
 +
|}
 +
 
 +
=== CPUID ===
 +
{| class="wikitable tc1 tc2 tc3 tc4"
 +
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 +
|-
 +
| rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
 +
|-
 +
| colspan="4" | Family 6 Model 102
 +
|}
 +
 
 +
== Architecture ==
 +
=== Key changes from {{\\|Skylake (client)|Skylake}} ===
 +
* [[10 nm process]] (from [[14 nm]])
 +
 
 +
* {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}})
 +
** ''See {{\\|Palm Cove}} for microarchitectural details and changes''
 +
 
 +
* Mainstream chipset
 +
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
 +
 
 +
* Mobile Processors
 +
** LPDDR4/LPDDR4X memory support (from LPDDR3)
 +
*** Rates up to 2400 MT/s
 +
 
 +
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 +
* {{intel|Gen10|l=arch}} GPUs
 +
** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
 +
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
 +
 
 +
* New Integration
 +
** New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
 +
 
 +
====New instructions ====
 +
Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm Cove § New Instructions|l=arch}} for details.
 +
 
 +
=== Block Diagram ===
 +
 
 +
==== Entire SoC Overview ====
 +
[[File:cannon lake soc block diagram.svg|800px]]
 +
 
 +
==== Individual Core ====
 +
See {{intel|Palm Cove#Block Diagram|Palm Cove § Block Diagram|l=arch}}.
 +
 
 +
==== Gen11 Graphics ====
 +
See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}.
 +
 
 +
== Die ==
 +
=== Dual-core ===
 +
* [[10 nm process]]
 +
* [[13 metal layers]]
 +
* ~8.2 mm x ~8.6 mm
 +
* ~70.52 mm² die size
 +
* 2 CPU cores + 40 GPU EUs
 +
 
 +
== All Cannon Lake Chips ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
  
−
| succession      = Yes
+
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
−
| predecessor      = Kaby Lake
+
-->
−
| predecessor link = intel/microarchitectures/kaby lake
+
{{comp table start}}
−
| successor        = Icelake
+
<table class="comptable sortable tc4 tc5 tc6">
−
| successor link  = intel/microarchitectures/icelake
+
{{comp table header|main|7:List of Cannon Lake-based Processors}}
 +
{{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}}
 +
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?first launched
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|format=template
 +
|template=proc table 3
 +
|userparam=9
 +
|mainlabel=-
 
}}
 
}}
−
'''Cannonlake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]].
+
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
== References ==
 +
* Some information was obtained directly from Intel.
 +
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 +
 
 +
== See also ==
 +
* AMD's {{amd|Zen|l=arch}}

Latest revision as of 11:53, 5 August 2019

Edit Values
Cannon Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMay 15, 2018
Process10 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way?
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512, AVX-512F, AVX-512CD, AVX-512BW, AVX-512DQ, AVX-512VL, AVX-512IFMA, AVX-512VBMI, SHA, UMIP
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Succession
Contemporary
Coffee Lake

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the second half of 2018. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Codenames[edit]

Core Abbrev Description Graphics Target
Cannon Lake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Release Dates[edit]

Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.

Process Technology[edit]

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannon
Lake 		Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch  42 nm  34 nm 0.81x
Fin Width​   8 nm   7 nm 0.88x
Fin Height​  42 nm  53 nm 1.24x
Gate Pitch  70 nm  54 nm 0.77x
Interconnect Pitch  52 nm  36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Compiler support[edit]

Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=cannonlake -mtune=cannonlake
GCC -march=cannonlake -mtune=cannonlake
LLVM -march=cannonlake -mtune=cannonlake
Visual Studio ? ?

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model
U 0 0x6 0x6 0x6
Family 6 Model 102

Architecture[edit]

Key changes from Skylake[edit]

  • Mobile Processors
    • LPDDR4/LPDDR4X memory support (from LPDDR3)
      • Rates up to 2400 MT/s
  • Gen9.5 → Gen10 graphics
  • Gen10 GPUs
    • HD Graphics 6xx (GT1) → UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from Skylake)
    • HD Graphics 6xx (GT2) → UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from Skylake)
  • New Integration
    • New Gaussian Neural Accelerator 1.0 (Unclear to what extent)

New instructions[edit]

Cannon Lake introduced a number of new instructions. See Palm Cove § New Instructions for details.

Block Diagram[edit]

Entire SoC Overview[edit]

800px

Individual Core[edit]

See Palm Cove § Block Diagram.

Gen11 Graphics[edit]

See Gen10 Graphics § Block Diagram.

Die[edit]

Dual-core[edit]

All Cannon Lake Chips[edit]

 List of Cannon Lake-based Processors
ModelPriceLaunchedCoresThreadsTDPFrequencyTurbo
i3-8121U15 May 20182415 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
M3-8114Y241.5 GHz
1,500 MHz
1,500,000 kHz
Count: 2

References[edit]

  • Some information was obtained directly from Intel.
  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=92852"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannon Lake +
core count2 +
designerIntel +
first launchedMay 15, 2018 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannon Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +