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{{intel title|Goldmont|arch}}
 
{{intel title|Goldmont|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
| name         = Goldmont
+
|atype=CPU
−
| manufacturer = Intel
+
|name=Goldmont
−
| introduction = 2016
+
|designer=Intel
−
| phase-out    =
+
|manufacturer=Intel
−
| process       = 14 nm
+
|introduction=August 30, 2016
−
| cores         = 2
+
|process=14 nm
−
| cores 2       = 4
+
|cores=2
−
| cores 3       = 8
+
|cores 2=4
 +
|cores 3=8
 +
|cores 4=12
 +
|cores 5=16
 +
|type=Superscalar
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages min=12
 +
|stages max=14
 +
|isa=x86-64
 +
|extension=MOVBE
 +
|extension 2=MMX
 +
|extension 3=SSE
 +
|extension 4=SSE2
 +
|extension 5=SSE3
 +
|extension 6=SSSE3
 +
|extension 7=SSE4.1
 +
|extension 8=SSE4.2
 +
|extension 9=POPCNT
 +
|extension 10=AES
 +
|extension 11=PCLMUL
 +
|extension 12=RDRND
 +
|extension 13=XSAVE
 +
|extension 14=XSAVEOPT
 +
|extension 15=FSGSBASE
 +
|extension 16=SHA
 +
|l1i=32 KiB
 +
|l1i per=Core
 +
|l1i desc=8-way set associative
 +
|l1d=24 KiB
 +
|l1d per=Core
 +
|l1d desc=6-way set associative
 +
|l2=1-2 MiB
 +
|l2 per=2 Cores
 +
|l2 desc=16-way set associative
 +
|core name=Apollo Lake
 +
|core name 2=Denverton
 +
|predecessor=Airmont
 +
|predecessor link=intel/microarchitectures/airmont
 +
|successor=Goldmont Plus
 +
|successor link=intel/microarchitectures/goldmont plus
 +
}}
 +
'''Goldmont''' ('''GLM''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices. Goldmont-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families. Goldmont superseded {{intel|Airmont}} in August of 2016. With Goldmont, Intel stopped targeting smartphones altogether, cancelling the related cores and SKUs.
 +
[[File:Atom E3900 SoC Front.png|right|thumb|250px|Intel Atom E3900 SoC series]]
 +
 
 +
== Codenames ==
 +
{| class="wikitable"
 +
|-
 +
! Platform !! Core !! Target
 +
|-
 +
| &nbsp; || {{intel|Apollo Lake|l=core}} || Entry-level PCs, Tablets
 +
|-
 +
| &nbsp; || {{intel|Denverton|l=core}} || Ultra-low power servers, networking, storage, and IoT
 +
|-
 +
| &nbsp; || style="text-decoration: line-through;" | {{intel|Willow Trail|l=core}} || style="text-decoration: line-through;" | Lightweight Tablets & high-end smartphone
 +
|- style="text-decoration: line-through;"
 +
| {{intel|Morganfield|l=platform}} || {{intel|Broxton|l=core}} || Smartphone
 +
|}
 +
 
 +
== Process Technology ==
 +
{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
 +
Goldmont-based chips are manufactured on Intel's [[14 nm process]].
 +
 
 +
== Architecture ==
 +
[[File:atom c3000 on a wafer.png|right|350px]]
 +
=== Key changes from {{intel|Airmont}} ===
 +
* Pipeline
 +
** Compared to Airmont, Goldmont is a 3-issue core.
 +
** NOPs, MOVs and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle).
 +
** ADC, SBB have 0.5 op/cycle throughput, unchanged from Airmont.
 +
** INC, DEC, BTx, shift ops are not faster than on Airmont, 8-bit shifts are slightly slower (0.66 op/cycle instead of 1).
 +
** Rotate-through-carry (RCL, RCR) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~12).
 +
** 16- and 64-bit shift-double (SHLD, SHRD) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~14) than on Airmont. (32-bit SHLD, SHRD are fast: 2-4 cycles).
 +
** Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles.
 +
** Bit scan (BSF, BSR) throughput improved from 10 to 8 cycles per op.
 +
** MUL throughput is better by 1 cycle (used to be 5/7 cycles for 32/64-bit mul, now 4/6).
 +
** DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles.
 +
** PUSH to POP forwarding is improved.
 +
** REP MOVS streaming copy is twice as fast: now ~26 bytes/cycle.
 +
** REP STOS fill is not improved: ~9 bytes/cycle.
 +
** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput >2 op/cycle. This includes often used ops like adds and multiplies:
 +
*** MULPS and MULPD have 4 cycle latency and 1 op/cycle throughput (used to have L5 and T0.5).
 +
*** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5).
 +
** CRC32 instruction throughput improved from 6 cycles/op to 1 cycle/op, latency is halved from 6 to 3.
 +
* Gen 9 GPUs
 +
** {{intel|HD Graphics 400}} '''→''' {{intel|HD Graphics 500}} (12 Execution Units, no change)
 +
** {{intel|HD Graphics 405}} '''→''' {{intel|HD Graphics 505}} (18 Execution Units, up from 16)
 +
 
 +
====New instructions ====
 +
Goldmont introduced a number of {{x86|extensions|new instructions}}:
 +
 
 +
* {{x86|RDSEED|<code>RDSEED</code>}} - Generates 16, 32 or 64 bit random numbers seeds ([[NIST SP 800-90B]] & [[NIST SP 800-90C]])
 +
* {{x86|SMAP|<code>SMAP</code>}} - Supervisor Mode Access Prevention
 +
* {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions
 +
* {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory
 +
* {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory.
 +
* {{x86|CLFLUSHOPT|<code>CLFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
 +
* {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations
 +
* FS/GS base access
 +
 
 +
=== Block Diagram ===
 +
{{empty section}}
  
−
| pipeline      = <!-- yes for following options -->
+
=== Memory Hierarchy ===
−
| type          = <!-- e.g. "Superscalar" -->
+
* Cache
−
| OoOE          = <!-- Yes or No only -->
+
** Hardware prefetchers
−
| speculative  = <!-- Yes or No only -->
+
** L1 Cache:
−
| renaming      = <!-- Yes or No only -->
+
*** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
−
| isa          =
+
*** 24 KiB 6-way set associative data, 64 B line size
−
| isa 2         =
+
*** Per core
−
| isa N        =
+
** L2 Cache:
−
| stages        =
+
*** 1 MiB 16-way set associative, 64 B line size
−
| issues        =
+
*** Per 2 cores
 +
*** 32B/cycle, 17 cycle latency
 +
** L3 Cache:
 +
*** No level 3 cache
 +
** RAM
 +
*** Maximum of 1 [[GiB]], 2 GiB, 4 GiB, 8 GiB
 +
*** dual 32-bit channels, 1 or 2 ranks per channel
  
−
| inst          = <!-- yes for instructions options -->
+
=== Multithreading ===
−
| feature      =  
+
Goldmont, like {{\\|Airmont}} has no support for Intel Hyper-Threading Technology.
−
| extension    =  
 
−
| extension 2  =  
 
−
| extension N  =
 
  
−
| cache        = <!-- yes for cache info -->
+
== Die Shot ==
−
| l1i          =
+
Intel {{intel|Atom}} E3900 SoC series:
−
| l1i per      =
+
:[[File:atom e3900 die shot.jpg|650px]]
−
| l1i desc      =
 
−
| l1d          =
 
−
| l1d per      =
 
−
| l1d desc      =
 
−
| l2            =
 
−
| l2  per      =
 
−
| l2  desc      =
 
  
−
| core names      = <!-- Yes if specify -->
+
== All Goldmont Chips ==
−
| core name        =
+
<!-- NOTE:
−
| core name 2      =
+
          This table is generated automatically from the data in the actual articles.
−
| core name N      =
+
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
  
−
| succession      = Yes
+
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
−
| predecessor      = Airmont
+
-->
−
| predecessor link = intel/microarchitectures/airmont
+
<table class="wikitable sortable">
−
| successor        =
+
<tr><th colspan="12" style="background:#D6D6FF;">Goldmont Chips</th></tr>
−
| successor link  =
+
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
 +
<tr><th>Model</th><th>Family</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
 +
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Goldmont]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?platform
 +
|?core name
 +
|?first launched
 +
|?sdp
 +
|?tdp
 +
|?base frequency
 +
|?max memory
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|?integrated gpu max frequency
 +
|format=template
 +
|template=proc table 2
 +
|userparam=13
 +
|mainlabel=-
 
}}
 
}}
−
'''Goldmont''' is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the {{intel|Atom|Atom family}}. Goldmont is set to be the successor to {{intel|Airmont}} in late 2016 or early 2017.
+
{{table count|col=12|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Goldmont]]}}
 +
</table>

Latest revision as of 22:05, 23 March 2020

Edit Values
Goldmont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionAugust 30, 2016
Process14 nm
Core Configs2, 4, 8, 12, 16
Pipeline
TypeSuperscalar
SpeculativeYes
Reg RenamingYes
Stages12-14
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, SHA
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache1-2 MiB/2 Cores
16-way set associative
Cores
Core NamesApollo Lake,
Denverton
Succession

Goldmont (GLM) is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices. Goldmont-based processors and SoCs are part of the Atom, Pentium, and Celeron families. Goldmont superseded Airmont in August of 2016. With Goldmont, Intel stopped targeting smartphones altogether, cancelling the related cores and SKUs.

Intel Atom E3900 SoC series

Codenames[edit]

Platform Core Target
  Apollo Lake Entry-level PCs, Tablets
  Denverton Ultra-low power servers, networking, storage, and IoT
  Willow Trail Lightweight Tablets & high-end smartphone
Morganfield Broxton Smartphone

Process Technology[edit]

Main article: Broadwell § Process Technology

Goldmont-based chips are manufactured on Intel's 14 nm process.

Architecture[edit]

atom c3000 on a wafer.png

Key changes from Airmont[edit]

  • Pipeline
    • Compared to Airmont, Goldmont is a 3-issue core.
    • NOPs, MOVs and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle).
    • ADC, SBB have 0.5 op/cycle throughput, unchanged from Airmont.
    • INC, DEC, BTx, shift ops are not faster than on Airmont, 8-bit shifts are slightly slower (0.66 op/cycle instead of 1).
    • Rotate-through-carry (RCL, RCR) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~12).
    • 16- and 64-bit shift-double (SHLD, SHRD) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~14) than on Airmont. (32-bit SHLD, SHRD are fast: 2-4 cycles).
    • Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles.
    • Bit scan (BSF, BSR) throughput improved from 10 to 8 cycles per op.
    • MUL throughput is better by 1 cycle (used to be 5/7 cycles for 32/64-bit mul, now 4/6).
    • DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles.
    • PUSH to POP forwarding is improved.
    • REP MOVS streaming copy is twice as fast: now ~26 bytes/cycle.
    • REP STOS fill is not improved: ~9 bytes/cycle.
    • Some vector instructions are faster, but like on Airmont, none have throughput >2 op/cycle. This includes often used ops like adds and multiplies:
      • MULPS and MULPD have 4 cycle latency and 1 op/cycle throughput (used to have L5 and T0.5).
      • ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5).
    • CRC32 instruction throughput improved from 6 cycles/op to 1 cycle/op, latency is halved from 6 to 3.
  • Gen 9 GPUs

New instructions[edit]

Goldmont introduced a number of new instructions:

  • RDSEED - Generates 16, 32 or 64 bit random numbers seeds (NIST SP 800-90B & NIST SP 800-90C)
  • SMAP - Supervisor Mode Access Prevention
  • MPX -Memory Protection Extensions
  • XSAVEC - Save processor extended states with compaction to memory
  • XSAVES - Save processor supervisor-mode extended states to memory.
  • CLFLUSHOPT - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
  • SHA - Hardware acceleration for SHA hashing operations
  • FS/GS base access

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

  • Cache
    • Hardware prefetchers
    • L1 Cache:
      • 32 KiB 8-way set associative instruction, 64 B line size
      • 24 KiB 6-way set associative data, 64 B line size
      • Per core
    • L2 Cache:
      • 1 MiB 16-way set associative, 64 B line size
      • Per 2 cores
      • 32B/cycle, 17 cycle latency
    • L3 Cache:
      • No level 3 cache
    • RAM
      • Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
      • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading[edit]

Goldmont, like Airmont has no support for Intel Hyper-Threading Technology.

Die Shot[edit]

Intel Atom E3900 SoC series:

atom e3900 die shot.jpg

All Goldmont Chips[edit]

Goldmont Chips
Main processorIGP
ModelFamilyPlatformCoreLaunchedSDPTDPFreqMax MemNameFreqMax Freq
C3308AtomDenverton15 August 20179.5 W
9,500 mW
0.0127 hp
0.0095 kW
1,600 MHz
1.6 GHz
1,600,000 kHz
131,072 MiB
134,217,728 KiB
137,438,953,472 B
128 GiB
0.125 TiB
C3338AtomDenverton22 February 20179 W
9,000 mW
0.0121 hp
0.009 kW
1,500 MHz
1.5 GHz
1,500,000 kHz
131,072 MiB
134,217,728 KiB
137,438,953,472 B
128 GiB
0.125 TiB
C3508AtomDenverton15 August 201711.25 W
11,250 mW
0.0151 hp
0.0113 kW
1,600 MHz
1.6 GHz
1,600,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3538AtomDenverton15 August 201715 W
15,000 mW
0.0201 hp
0.015 kW
2,100 MHz
2.1 GHz
2,100,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3558AtomDenverton15 August 201716 W
16,000 mW
0.0215 hp
0.016 kW
2,200 MHz
2.2 GHz
2,200,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3708AtomDenverton15 August 201717 W
17,000 mW
0.0228 hp
0.017 kW
1,700 MHz
1.7 GHz
1,700,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3750AtomDenverton15 August 201721 W
21,000 mW
0.0282 hp
0.021 kW
2,200 MHz
2.2 GHz
2,200,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3758AtomDenverton15 August 201725 W
25,000 mW
0.0335 hp
0.025 kW
2,200 MHz
2.2 GHz
2,200,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3808AtomDenverton15 August 201725 W
25,000 mW
0.0335 hp
0.025 kW
2,000 MHz
2 GHz
2,000,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3830AtomDenverton15 August 201721 W
21,000 mW
0.0282 hp
0.021 kW
1,900 MHz
1.9 GHz
1,900,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3850AtomDenverton15 August 201725 W
25,000 mW
0.0335 hp
0.025 kW
2,100 MHz
2.1 GHz
2,100,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3858AtomDenverton15 August 201725 W
25,000 mW
0.0335 hp
0.025 kW
2,000 MHz
2 GHz
2,000,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3950AtomDenverton15 August 201724 W
24,000 mW
0.0322 hp
0.024 kW
1,700 MHz
1.7 GHz
1,700,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3955AtomDenverton15 August 201732 W
32,000 mW
0.0429 hp
0.032 kW
2,100 MHz
2.1 GHz
2,100,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
C3958AtomDenverton15 August 201731 W
31,000 mW
0.0416 hp
0.031 kW
2,000 MHz
2 GHz
2,000,000 kHz
262,144 MiB
268,435,456 KiB
274,877,906,944 B
256 GiB
0.25 TiB
x5-E3930Atom x5Apollo LakeApollo Lake20176.5 W
6,500 mW
0.00872 hp
0.0065 kW
1,300 MHz
1.3 GHz
1,300,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 500400 MHz
0.4 GHz
400,000 KHz
550 MHz
0.55 GHz
550,000 KHz
x5-E3940Atom x5Apollo LakeApollo Lake20179.5 W
9,500 mW
0.0127 hp
0.0095 kW
1,600 MHz
1.6 GHz
1,600,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 500400 MHz
0.4 GHz
400,000 KHz
600 MHz
0.6 GHz
600,000 KHz
x7-E3950Atom x7Apollo LakeApollo Lake201712 W
12,000 mW
0.0161 hp
0.012 kW
1,600 MHz
1.6 GHz
1,600,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 505500 MHz
0.5 GHz
500,000 KHz
650 MHz
0.65 GHz
650,000 KHz
J3355CeleronApollo Lake30 August 201610 W
10,000 mW
0.0134 hp
0.01 kW
2,000 MHz
2 GHz
2,000,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 500250 MHz
0.25 GHz
250,000 KHz
700 MHz
0.7 GHz
700,000 KHz
J3455CeleronApollo Lake30 August 201610 W
10,000 mW
0.0134 hp
0.01 kW
1,500 MHz
1.5 GHz
1,500,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 500250 MHz
0.25 GHz
250,000 KHz
750 MHz
0.75 GHz
750,000 KHz
N3350CeleronApollo Lake30 August 20164 W
4,000 mW
0.00536 hp
0.004 kW
6 W
6,000 mW
0.00805 hp
0.006 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 500200 MHz
0.2 GHz
200,000 KHz
650 MHz
0.65 GHz
650,000 KHz
N3450CeleronApollo Lake30 August 20164 W
4,000 mW
0.00536 hp
0.004 kW
6 W
6,000 mW
0.00805 hp
0.006 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 500200 MHz
0.2 GHz
200,000 KHz
700 MHz
0.7 GHz
700,000 KHz
J4205PentiumApollo Lake30 August 201610 W
10,000 mW
0.0134 hp
0.01 kW
1,500 MHz
1.5 GHz
1,500,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 505250 MHz
0.25 GHz
250,000 KHz
800 MHz
0.8 GHz
800,000 KHz
N4200PentiumApollo Lake30 August 20164 W
4,000 mW
0.00536 hp
0.004 kW
6 W
6,000 mW
0.00805 hp
0.006 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
8,192 MiB
8,388,608 KiB
8,589,934,592 B
8 GiB
0.00781 TiB
HD Graphics 505200 MHz
0.2 GHz
200,000 KHz
750 MHz
0.75 GHz
750,000 KHz
Count: 24
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