|Introduction||August 15, 2017 (announced)|
August 15, 2017 (launched)
|Turbo Frequency||2,400 MHz (1 core)|
|Word Size||64 bit|
|Max CPUs||1 (Uniprocessor)|
|Max Memory||256 GiB|
|Tjunction||0 °C – 100 °C|
|Tcase||0 °C – 78 °C|
|Tstorage||-25 °C – 125 °C|
|Dimension||34 mm x 28 mm|
Atom C3955 is a 64-bit hexadeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3955, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.1 GHz with a TDP of 32 W and a turbo boost frequency of up to 2.4 GHz. The C3955 supports up to 256 GiB of dual-channel DDR4-2400 ECC memory. This model is part of Denverton's Server and Cloud Storage SKUs.
- Main article: Goldmont § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|16x32 KiB||8-way set associative||write-back|
|16x24 KiB||6-way set associative||write-back|
| || ||8x2 MiB||16-way set associative||write-back|
[Edit/Modify Memory Info]
Integrated Memory Controller
|Max Type||DDR3L-1600, DDR4-2400|
|Max Mem||256 GiB|
|Max Bandwidth||35.76 GiB/s|
Single 17.88 GiB/s
Double 35.76 GiB/s
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following: